KMAC/MASKED Simulation Results

Wednesday May 07 2025 18:36:24 UTC

GitHub Revision: 3add6b6

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	10.720s	1.308ms	1	1	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	1.680s	29.652us	1	1	100.00
V1	csr_rw	kmac_csr_rw	1.850s	26.993us	1	1	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	11.150s	290.668us	1	1	100.00
V1	csr_aliasing	kmac_csr_aliasing	3.940s	282.666us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	2.780s	68.724us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	1.850s	26.993us	1	1	100.00
		kmac_csr_aliasing	3.940s	282.666us	1	1	100.00
V1	mem_walk	kmac_mem_walk	2.000s	27.739us	1	1	100.00
V1	mem_partial_access	kmac_mem_partial_access	2.390s	174.784us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	8.563m	26.482ms	1	1	100.00
V2	burst_write	kmac_burst_write	3.679m	19.329ms	1	1	100.00
V2	test_vectors	kmac_test_vectors_sha3_224	31.836m	84.111ms	1	1	100.00
		kmac_test_vectors_sha3_256	29.370s	1.493ms	1	1	100.00
		kmac_test_vectors_sha3_384	21.981m	46.561ms	1	1	100.00
		kmac_test_vectors_sha3_512	15.490s	2.228ms	1	1	100.00
		kmac_test_vectors_shake_128	3.513m	17.505ms	1	1	100.00
		kmac_test_vectors_shake_256	5.389m	84.774ms	1	1	100.00
		kmac_test_vectors_kmac	3.610s	40.625us	1	1	100.00
		kmac_test_vectors_kmac_xof	3.190s	73.807us	1	1	100.00
V2	sideload	kmac_sideload	3.523m	12.417ms	1	1	100.00
V2	app	kmac_app	3.284m	42.865ms	1	1	100.00
V2	app_with_partial_data	kmac_app_with_partial_data	27.750s	2.638ms	1	1	100.00
V2	entropy_refresh	kmac_entropy_refresh	1.619m	18.756ms	1	1	100.00
V2	error	kmac_error	43.530s	4.231ms	1	1	100.00
V2	key_error	kmac_key_error	9.770s	1.194ms	1	1	100.00
V2	sideload_invalid	kmac_sideload_invalid	5.550s	169.934us	1	1	100.00
V2	edn_timeout_error	kmac_edn_timeout_error	38.740s	1.470ms	1	1	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	2.260s	31.215us	1	1	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	58.610s	31.713ms	1	1	100.00
V2	lc_escalation	kmac_lc_escalation	2.300s	321.335us	1	1	100.00
V2	stress_all	kmac_stress_all	3.600s	98.999us	1	1	100.00
V2	intr_test	kmac_intr_test	1.640s	96.847us	1	1	100.00
V2	alert_test	kmac_alert_test	1.640s	12.511us	1	1	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	3.390s	1.228ms	1	1	100.00
V2	tl_d_illegal_access	kmac_tl_errors	3.390s	1.228ms	1	1	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	1.680s	29.652us	1	1	100.00
		kmac_csr_rw	1.850s	26.993us	1	1	100.00
		kmac_csr_aliasing	3.940s	282.666us	1	1	100.00
		kmac_same_csr_outstanding	2.310s	87.237us	1	1	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	1.680s	29.652us	1	1	100.00
		kmac_csr_rw	1.850s	26.993us	1	1	100.00
		kmac_csr_aliasing	3.940s	282.666us	1	1	100.00
		kmac_same_csr_outstanding	2.310s	87.237us	1	1	100.00
V2		TOTAL			26	26	100.00
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	2.240s	274.369us	1	1	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	2.240s	274.369us	1	1	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	2.240s	274.369us	1	1	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	2.240s	274.369us	1	1	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	3.600s	322.877us	1	1	100.00
V2S	tl_intg_err	kmac_sec_cm	1.060m	7.142ms	1	1	100.00
		kmac_tl_intg_err	1.780s	16.656us	0	1	0.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	1.780s	16.656us	0	1	0.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	2.300s	321.335us	1	1	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	10.720s	1.308ms	1	1	100.00
V2S	sec_cm_key_sideload	kmac_sideload	3.523m	12.417ms	1	1	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	2.240s	274.369us	1	1	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	1.060m	7.142ms	1	1	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	1.060m	7.142ms	1	1	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	1.060m	7.142ms	1	1	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	10.720s	1.308ms	1	1	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	2.300s	321.335us	1	1	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	1.060m	7.142ms	1	1	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	3.127m	41.067ms	1	1	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	10.720s	1.308ms	1	1	100.00
V2S		TOTAL			4	5	80.00
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	2.160s	37.628us	0	1	0.00
V3		TOTAL			0	1	0.00
		TOTAL			38	40	95.00

Failure Buckets

• UVM_ERROR (kmac_scoreboard.sv:1202) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: kmac_reg_block.err_code has 1 failures:

  • Test kmac_stress_all_with_rand_reset has 1 failures.

    • 0.kmac_stress_all_with_rand_reset.109681861830924934460418964098744257011974820655296305966877591791755014230645
      Line 80, in log /nightly/runs/scratch/master/kmac_masked-sim-vcs/0.kmac_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @  37628350 ps: (kmac_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483664 [0x80000010]) reg name: kmac_reg_block.err_code
        UVM_INFO @  37628350 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Offending '(d2h.d_error || ((d2h.d_data & *) == (exp_vals[*] & *)))' has 1 failures:

  • Test kmac_tl_intg_err has 1 failures.

    • 0.kmac_tl_intg_err.72074812298696840204761319926815536555151795417818355775003970995366542483779
      Line 75, in log /nightly/runs/scratch/master/kmac_masked-sim-vcs/0.kmac_tl_intg_err/latest/run.log

            Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[48] & 'hffffffff)))'
        UVM_ERROR @  16656283 ps: (kmac_csr_assert_fpv.sv:537) [ASSERT FAILED] prefix_9_rd_A
        UVM_INFO @  16656283 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---