KMAC/UNMASKED Simulation Results

Wednesday May 07 2025 18:36:24 UTC

GitHub Revision: 3add6b6

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	30.730s	814.120us	1	1	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	2.160s	20.011us	1	1	100.00
V1	csr_rw	kmac_csr_rw	1.520s	21.287us	1	1	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	10.650s	299.615us	1	1	100.00
V1	csr_aliasing	kmac_csr_aliasing	6.710s	149.193us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	2.250s	152.956us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	1.520s	21.287us	1	1	100.00
		kmac_csr_aliasing	6.710s	149.193us	1	1	100.00
V1	mem_walk	kmac_mem_walk	1.870s	29.315us	1	1	100.00
V1	mem_partial_access	kmac_mem_partial_access	2.620s	64.957us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	7.021m	7.543ms	1	1	100.00
V2	burst_write	kmac_burst_write	5.091m	14.800ms	1	1	100.00
V2	test_vectors	kmac_test_vectors_sha3_224	19.782m	18.066ms	1	1	100.00
		kmac_test_vectors_sha3_256	29.980s	9.955ms	1	1	100.00
		kmac_test_vectors_sha3_384	16.110s	1.730ms	1	1	100.00
		kmac_test_vectors_sha3_512	8.910m	17.783ms	1	1	100.00
		kmac_test_vectors_shake_128	2.354m	13.269ms	1	1	100.00
		kmac_test_vectors_shake_256	1.159m	11.149ms	1	1	100.00
		kmac_test_vectors_kmac	3.770s	145.586us	1	1	100.00
		kmac_test_vectors_kmac_xof	3.250s	113.228us	1	1	100.00
V2	sideload	kmac_sideload	3.539m	45.899ms	1	1	100.00
V2	app	kmac_app	24.120s	6.160ms	1	1	100.00
V2	app_with_partial_data	kmac_app_with_partial_data	23.400s	5.923ms	1	1	100.00
V2	entropy_refresh	kmac_entropy_refresh	29.450s	1.797ms	1	1	100.00
V2	error	kmac_error	18.970s	823.840us	1	1	100.00
V2	key_error	kmac_key_error	3.820s	789.081us	1	1	100.00
V2	sideload_invalid	kmac_sideload_invalid	23.200s	10.253ms	0	1	0.00
V2	edn_timeout_error	kmac_edn_timeout_error	19.790s	20.059ms	1	1	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	7.290s	1.309ms	1	1	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	27.470s	11.839ms	1	1	100.00
V2	lc_escalation	kmac_lc_escalation	2.760s	80.912us	1	1	100.00
V2	stress_all	kmac_stress_all	15.321m	551.422ms	1	1	100.00
V2	intr_test	kmac_intr_test	1.940s	33.843us	1	1	100.00
V2	alert_test	kmac_alert_test	2.160s	30.922us	1	1	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	3.380s	445.236us	1	1	100.00
V2	tl_d_illegal_access	kmac_tl_errors	3.380s	445.236us	1	1	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	2.160s	20.011us	1	1	100.00
		kmac_csr_rw	1.520s	21.287us	1	1	100.00
		kmac_csr_aliasing	6.710s	149.193us	1	1	100.00
		kmac_same_csr_outstanding	3.100s	224.472us	1	1	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	2.160s	20.011us	1	1	100.00
		kmac_csr_rw	1.520s	21.287us	1	1	100.00
		kmac_csr_aliasing	6.710s	149.193us	1	1	100.00
		kmac_same_csr_outstanding	3.100s	224.472us	1	1	100.00
V2		TOTAL			25	26	96.15
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	2.660s	418.052us	1	1	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	2.660s	418.052us	1	1	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	2.660s	418.052us	1	1	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	2.660s	418.052us	1	1	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	5.700s	248.008us	1	1	100.00
V2S	tl_intg_err	kmac_sec_cm	52.760s	6.469ms	1	1	100.00
		kmac_tl_intg_err	1.860s	12.139us	0	1	0.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	1.860s	12.139us	0	1	0.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	2.760s	80.912us	1	1	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	30.730s	814.120us	1	1	100.00
V2S	sec_cm_key_sideload	kmac_sideload	3.539m	45.899ms	1	1	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	2.660s	418.052us	1	1	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	52.760s	6.469ms	1	1	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	52.760s	6.469ms	1	1	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	52.760s	6.469ms	1	1	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	30.730s	814.120us	1	1	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	2.760s	80.912us	1	1	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	52.760s	6.469ms	1	1	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	32.590s	6.779ms	1	1	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	30.730s	814.120us	1	1	100.00
V2S		TOTAL			4	5	80.00
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	24.650s	16.925ms	0	1	0.00
V3		TOTAL			0	1	0.00
		TOTAL			37	40	92.50

Failure Buckets

• UVM_FATAL (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=12) has 1 failures:

  • Test kmac_sideload_invalid has 1 failures.

    • 0.kmac_sideload_invalid.55919473773044338332481301318349483140464058675902338778048967519860652716378
      Line 84, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/0.kmac_sideload_invalid/latest/run.log

        UVM_FATAL @ 10252971994 ps: (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=0xc9d6d000, Comparison=CompareOpEq, exp_data=0x1, call_count=12)
        UVM_INFO @ 10252971994 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (kmac_scoreboard.sv:1202) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: kmac_reg_block.err_code has 1 failures:

  • Test kmac_stress_all_with_rand_reset has 1 failures.

    • 0.kmac_stress_all_with_rand_reset.48321703133498684864596327921890896806077558557464194373255399983548032620934
      Line 103, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/0.kmac_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 16924684120 ps: (kmac_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483672 [0x80000018]) reg name: kmac_reg_block.err_code
        UVM_INFO @ 16924684120 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Offending '(d2h.d_error || ((d2h.d_data & *) == (exp_vals[*] & *)))' has 1 failures:

  • Test kmac_tl_intg_err has 1 failures.

    • 0.kmac_tl_intg_err.41282982985231913945552630922376331151047808468576001534100063422010535338641
      Line 79, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/0.kmac_tl_intg_err/latest/run.log

            Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[41] & 'hffffffff)))'
        UVM_ERROR @  12138544 ps: (kmac_csr_assert_fpv.sv:502) [ASSERT FAILED] prefix_2_rd_A
        UVM_INFO @  12138544 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---