OTBN Simulation Results

Wednesday May 07 2025 18:36:24 UTC

GitHub Revision: 3add6b6

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	otbn_smoke	26.000s	119.425us	1	1	100.00
V1	single_binary	otbn_single	9.000s	14.814us	1	1	100.00
V1	csr_hw_reset	otbn_csr_hw_reset	6.000s	14.644us	1	1	100.00
V1	csr_rw	otbn_csr_rw	6.000s	22.384us	1	1	100.00
V1	csr_bit_bash	otbn_csr_bit_bash	6.000s	306.141us	1	1	100.00
V1	csr_aliasing	otbn_csr_aliasing	7.000s	21.572us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	otbn_csr_mem_rw_with_rand_reset	7.000s	43.460us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	otbn_csr_rw	6.000s	22.384us	1	1	100.00
		otbn_csr_aliasing	7.000s	21.572us	1	1	100.00
V1	mem_walk	otbn_mem_walk	17.000s	908.871us	1	1	100.00
V1	mem_partial_access	otbn_mem_partial_access	12.000s	488.100us	1	1	100.00
V1		TOTAL			9	9	100.00
V2	reset_recovery	otbn_reset	17.000s	78.884us	1	1	100.00
V2	multi_error	otbn_multi_err	44.000s	142.078us	1	1	100.00
V2	back_to_back	otbn_multi	33.000s	500.268us	1	1	100.00
V2	stress_all	otbn_stress_all	48.000s	613.159us	1	1	100.00
V2	lc_escalation	otbn_escalate	11.000s	31.086us	1	1	100.00
V2	zero_state_err_urnd	otbn_zero_state_err_urnd	8.000s	24.501us	1	1	100.00
V2	sw_errs_fatal_chk	otbn_sw_errs_fatal_chk	13.000s	48.121us	1	1	100.00
V2	alert_test	otbn_alert_test	6.000s	23.604us	1	1	100.00
V2	intr_test	otbn_intr_test	5.000s	37.986us	1	1	100.00
V2	tl_d_oob_addr_access	otbn_tl_errors	7.000s	29.049us	1	1	100.00
V2	tl_d_illegal_access	otbn_tl_errors	7.000s	29.049us	1	1	100.00
V2	tl_d_outstanding_access	otbn_csr_hw_reset	6.000s	14.644us	1	1	100.00
		otbn_csr_rw	6.000s	22.384us	1	1	100.00
		otbn_csr_aliasing	7.000s	21.572us	1	1	100.00
		otbn_same_csr_outstanding	7.000s	18.194us	1	1	100.00
V2	tl_d_partial_access	otbn_csr_hw_reset	6.000s	14.644us	1	1	100.00
		otbn_csr_rw	6.000s	22.384us	1	1	100.00
		otbn_csr_aliasing	7.000s	21.572us	1	1	100.00
		otbn_same_csr_outstanding	7.000s	18.194us	1	1	100.00
V2		TOTAL			11	11	100.00
V2S	mem_integrity	otbn_imem_err	8.000s	53.792us	1	1	100.00
		otbn_dmem_err	11.000s	29.440us	1	1	100.00
V2S	internal_integrity	otbn_alu_bignum_mod_err	11.000s	176.533us	1	1	100.00
		otbn_controller_ispr_rdata_err	8.000s	99.797us	1	1	100.00
		otbn_mac_bignum_acc_err	10.000s	28.040us	1	1	100.00
		otbn_urnd_err	9.000s	196.934us	1	1	100.00
V2S	illegal_bus_access	otbn_illegal_mem_acc	8.000s	23.976us	1	1	100.00
V2S	otbn_mem_gnt_acc_err	otbn_mem_gnt_acc_err	8.000s	18.658us	1	1	100.00
V2S	otbn_non_sec_partial_wipe	otbn_partial_wipe	8.000s	46.603us	1	1	100.00
V2S	tl_intg_err	otbn_sec_cm	12.000s	208.915us	0	1	0.00
		otbn_tl_intg_err	19.000s	117.054us	1	1	100.00
V2S	passthru_mem_tl_intg_err	otbn_passthru_mem_tl_intg_err	13.000s	349.896us	1	1	100.00
V2S	prim_fsm_check	otbn_sec_cm	12.000s	208.915us	0	1	0.00
V2S	prim_count_check	otbn_sec_cm	12.000s	208.915us	0	1	0.00
V2S	sec_cm_mem_scramble	otbn_smoke	26.000s	119.425us	1	1	100.00
V2S	sec_cm_data_mem_integrity	otbn_dmem_err	11.000s	29.440us	1	1	100.00
V2S	sec_cm_instruction_mem_integrity	otbn_imem_err	8.000s	53.792us	1	1	100.00
V2S	sec_cm_bus_integrity	otbn_tl_intg_err	19.000s	117.054us	1	1	100.00
V2S	sec_cm_controller_fsm_global_esc	otbn_escalate	11.000s	31.086us	1	1	100.00
V2S	sec_cm_controller_fsm_local_esc	otbn_imem_err	8.000s	53.792us	1	1	100.00
		otbn_dmem_err	11.000s	29.440us	1	1	100.00
		otbn_zero_state_err_urnd	8.000s	24.501us	1	1	100.00
		otbn_illegal_mem_acc	8.000s	23.976us	1	1	100.00
		otbn_sec_cm	12.000s	208.915us	0	1	0.00
V2S	sec_cm_controller_fsm_sparse	otbn_sec_cm	12.000s	208.915us	0	1	0.00
V2S	sec_cm_scramble_key_sideload	otbn_single	9.000s	14.814us	1	1	100.00
V2S	sec_cm_scramble_ctrl_fsm_local_esc	otbn_imem_err	8.000s	53.792us	1	1	100.00
		otbn_dmem_err	11.000s	29.440us	1	1	100.00
		otbn_zero_state_err_urnd	8.000s	24.501us	1	1	100.00
		otbn_illegal_mem_acc	8.000s	23.976us	1	1	100.00
		otbn_sec_cm	12.000s	208.915us	0	1	0.00
V2S	sec_cm_scramble_ctrl_fsm_sparse	otbn_sec_cm	12.000s	208.915us	0	1	0.00
V2S	sec_cm_start_stop_ctrl_fsm_global_esc	otbn_escalate	11.000s	31.086us	1	1	100.00
V2S	sec_cm_start_stop_ctrl_fsm_local_esc	otbn_imem_err	8.000s	53.792us	1	1	100.00
		otbn_dmem_err	11.000s	29.440us	1	1	100.00
		otbn_zero_state_err_urnd	8.000s	24.501us	1	1	100.00
		otbn_illegal_mem_acc	8.000s	23.976us	1	1	100.00
		otbn_sec_cm	12.000s	208.915us	0	1	0.00
V2S	sec_cm_start_stop_ctrl_fsm_sparse	otbn_sec_cm	12.000s	208.915us	0	1	0.00
V2S	sec_cm_data_reg_sw_sca	otbn_single	9.000s	14.814us	1	1	100.00
V2S	sec_cm_ctrl_redun	otbn_ctrl_redun	8.000s	51.170us	1	1	100.00
V2S	sec_cm_pc_ctrl_flow_redun	otbn_pc_ctrl_flow_redun	7.000s	17.428us	1	1	100.00
V2S	sec_cm_rnd_bus_consistency	otbn_rnd_sec_cm	26.000s	382.337us	1	1	100.00
V2S	sec_cm_rnd_rng_digest	otbn_rnd_sec_cm	26.000s	382.337us	1	1	100.00
V2S	sec_cm_rf_base_data_reg_sw_integrity	otbn_rf_base_intg_err	9.000s	67.672us	1	1	100.00
V2S	sec_cm_rf_base_data_reg_sw_glitch_detect	otbn_sec_cm	12.000s	208.915us	0	1	0.00
V2S	sec_cm_stack_wr_ptr_ctr_redun	otbn_sec_cm	12.000s	208.915us	0	1	0.00
V2S	sec_cm_rf_bignum_data_reg_sw_integrity	otbn_rf_bignum_intg_err	8.000s	115.768us	1	1	100.00
V2S	sec_cm_rf_bignum_data_reg_sw_glitch_detect	otbn_sec_cm	12.000s	208.915us	0	1	0.00
V2S	sec_cm_loop_stack_ctr_redun	otbn_sec_cm	12.000s	208.915us	0	1	0.00
V2S	sec_cm_loop_stack_addr_integrity	otbn_stack_addr_integ_chk	9.000s	19.066us	1	1	100.00
V2S	sec_cm_call_stack_addr_integrity	otbn_stack_addr_integ_chk	9.000s	19.066us	1	1	100.00
V2S	sec_cm_start_stop_ctrl_state_consistency	otbn_sec_wipe_err	7.000s	15.787us	1	1	100.00
V2S	sec_cm_data_mem_sec_wipe	otbn_single	9.000s	14.814us	1	1	100.00
V2S	sec_cm_instruction_mem_sec_wipe	otbn_single	9.000s	14.814us	1	1	100.00
V2S	sec_cm_data_reg_sw_sec_wipe	otbn_single	9.000s	14.814us	1	1	100.00
V2S	sec_cm_write_mem_integrity	otbn_multi	33.000s	500.268us	1	1	100.00
V2S	sec_cm_ctrl_flow_count	otbn_single	9.000s	14.814us	1	1	100.00
V2S	sec_cm_ctrl_flow_sca	otbn_single	9.000s	14.814us	1	1	100.00
V2S	sec_cm_data_mem_sw_noaccess	otbn_sw_no_acc	15.000s	47.634us	1	1	100.00
V2S	sec_cm_key_sideload	otbn_single	9.000s	14.814us	1	1	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	otbn_sec_cm	12.000s	208.915us	0	1	0.00
V2S		TOTAL			19	20	95.00
V3	stress_all_with_rand_reset	otbn_stress_all_with_rand_reset	31.000s	161.334us	0	1	0.00
V3		TOTAL			0	1	0.00
		TOTAL			39	41	95.12

Failure Buckets

• UVM_FATAL (otbn_base_vseq.sv:348) [otbn_dmem_err_vseq] Check failed (!cfg.under_reset) has 1 failures:

  • Test otbn_stress_all_with_rand_reset has 1 failures.

    • 0.otbn_stress_all_with_rand_reset.3163848645159699369079967938471487959595916755347351886333139723988037387050
      Line 157, in log /nightly/runs/scratch/master/otbn-sim-xcelium/0.otbn_stress_all_with_rand_reset/latest/run.log

        UVM_FATAL @ 161334401 ps: (otbn_base_vseq.sv:348) [uvm_test_top.env.virtual_sequencer.otbn_dmem_err_vseq] Check failed (!cfg.under_reset)
        UVM_INFO @ 161334401 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• xmsim: *E,ASRTST (/nightly/runs/scratch/master/otbn-sim-xcelium/default/src/lowrisc_ip_otbn_*/rtl/otbn.sv,1383): Assertion ErrBitsKnown_A has failed has 1 failures:

  • Test otbn_sec_cm has 1 failures.

    • 0.otbn_sec_cm.102726092979180006428232378065479076654243131901670239743027691355342279009107
      Line 122, in log /nightly/runs/scratch/master/otbn-sim-xcelium/0.otbn_sec_cm/latest/run.log

        xmsim: *E,ASRTST (/nightly/runs/scratch/master/otbn-sim-xcelium/default/src/lowrisc_ip_otbn_0.1/rtl/otbn.sv,1383): (time 208915072 PS) Assertion tb.dut.ErrBitsKnown_A has failed
        xmsim: *E,ASRTST (/nightly/runs/scratch/master/otbn-sim-xcelium/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,960): (time 208915072 PS) Assertion tb.dut.u_otbn_core.ErrBitsKnown_A has failed
        UVM_ERROR @ 208915072 ps: (otbn.sv:1383) [ASSERT FAILED] ErrBitsKnown_A
        UVM_INFO @ 208915072 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---