PATTGEN Simulation Results

Wednesday May 07 2025 18:36:24 UTC

GitHub Revision: 3add6b6

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	pattgen_smoke	14.000s	224.558us	1	1	100.00
V1	csr_hw_reset	pattgen_csr_hw_reset	4.000s	60.738us	1	1	100.00
V1	csr_rw	pattgen_csr_rw	4.000s	155.851us	1	1	100.00
V1	csr_bit_bash	pattgen_csr_bit_bash	5.000s	37.633us	1	1	100.00
V1	csr_aliasing	pattgen_csr_aliasing	4.000s	127.899us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	pattgen_csr_mem_rw_with_rand_reset	3.000s	119.419us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	pattgen_csr_rw	4.000s	155.851us	1	1	100.00
		pattgen_csr_aliasing	4.000s	127.899us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	perf	pattgen_perf			0	1	0.00
V2	cnt_rollover	cnt_rollover	11.000s	900.024us	1	1	100.00
V2	error	pattgen_error	11.000s	29.197us	1	1	100.00
V2	stress_all	pattgen_stress_all	8.000s	232.209us	1	1	100.00
V2	alert_test	pattgen_alert_test	7.000s	38.572us	1	1	100.00
V2	intr_test	pattgen_intr_test	4.000s	13.929us	1	1	100.00
V2	tl_d_oob_addr_access	pattgen_tl_errors	7.000s	76.490us	1	1	100.00
V2	tl_d_illegal_access	pattgen_tl_errors	7.000s	76.490us	1	1	100.00
V2	tl_d_outstanding_access	pattgen_csr_hw_reset	4.000s	60.738us	1	1	100.00
		pattgen_csr_rw	4.000s	155.851us	1	1	100.00
		pattgen_csr_aliasing	4.000s	127.899us	1	1	100.00
		pattgen_same_csr_outstanding	4.000s	15.201us	1	1	100.00
V2	tl_d_partial_access	pattgen_csr_hw_reset	4.000s	60.738us	1	1	100.00
		pattgen_csr_rw	4.000s	155.851us	1	1	100.00
		pattgen_csr_aliasing	4.000s	127.899us	1	1	100.00
		pattgen_same_csr_outstanding	4.000s	15.201us	1	1	100.00
V2		TOTAL			7	8	87.50
V2S	tl_intg_err	pattgen_tl_intg_err	4.000s	52.079us	1	1	100.00
		pattgen_sec_cm	9.000s	136.208us	1	1	100.00
V2S	sec_cm_bus_integrity	pattgen_tl_intg_err	4.000s	52.079us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	stress_all_with_rand_reset	pattgen_stress_all_with_rand_reset	47.000s	4.435ms	0	1	0.00
V3		TOTAL			0	1	0.00
	Unmapped tests	pattgen_inactive_level	9.000s	48.847us	1	1	100.00
		TOTAL			16	18	88.89

Failure Buckets

• Job timed out after * minutes has 1 failures:

  • Test pattgen_perf has 1 failures.

    • 0.pattgen_perf.106133805943533275668609071617508577438201041121314819790412122410487883614145
      Log /nightly/runs/scratch/master/pattgen-sim-xcelium/0.pattgen_perf/latest/run.log

        Job timed out after 60 minutes
      

• UVM_ERROR (cip_base_vseq.sv:929) [pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:

  • Test pattgen_stress_all_with_rand_reset has 1 failures.

    • 0.pattgen_stress_all_with_rand_reset.41626099754651725418383464189262199481222077946846231824907196521336013645986
      Line 228, in log /nightly/runs/scratch/master/pattgen-sim-xcelium/0.pattgen_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 2463908098 ps: (cip_base_vseq.sv:929) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_ERROR @ 2463911789 ps: (cip_base_vseq.sv:833) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
        UVM_INFO @ 2463911789 ps: (cip_base_vseq.sv:836) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
        Issuing reset for run 4/10
        UVM_INFO @ 2463931991 ps: (cip_base_vseq.sv:857) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]