ROM_CTRL/32KB Simulation Results

Wednesday May 07 2025 18:36:24 UTC

GitHub Revision: 3add6b6

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	rom_ctrl_smoke	5.010s	238.548us	1	1	100.00
V1	csr_hw_reset	rom_ctrl_csr_hw_reset	6.770s	131.319us	1	1	100.00
V1	csr_rw	rom_ctrl_csr_rw	6.100s	173.245us	1	1	100.00
V1	csr_bit_bash	rom_ctrl_csr_bit_bash	4.980s	133.667us	1	1	100.00
V1	csr_aliasing	rom_ctrl_csr_aliasing	4.810s	558.020us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	rom_ctrl_csr_mem_rw_with_rand_reset	5.430s	178.721us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rom_ctrl_csr_rw	6.100s	173.245us	1	1	100.00
		rom_ctrl_csr_aliasing	4.810s	558.020us	1	1	100.00
V1	mem_walk	rom_ctrl_mem_walk	5.010s	209.808us	1	1	100.00
V1	mem_partial_access	rom_ctrl_mem_partial_access	4.880s	388.919us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	max_throughput_chk	rom_ctrl_max_throughput_chk	5.380s	140.502us	1	1	100.00
V2	stress_all	rom_ctrl_stress_all	16.650s	2.183ms	1	1	100.00
V2	kmac_err_chk	rom_ctrl_kmac_err_chk	10.340s	397.154us	1	1	100.00
V2	alert_test	rom_ctrl_alert_test	4.390s	537.939us	1	1	100.00
V2	tl_d_oob_addr_access	rom_ctrl_tl_errors	9.110s	298.991us	1	1	100.00
V2	tl_d_illegal_access	rom_ctrl_tl_errors	9.110s	298.991us	1	1	100.00
V2	tl_d_outstanding_access	rom_ctrl_csr_hw_reset	6.770s	131.319us	1	1	100.00
		rom_ctrl_csr_rw	6.100s	173.245us	1	1	100.00
		rom_ctrl_csr_aliasing	4.810s	558.020us	1	1	100.00
		rom_ctrl_same_csr_outstanding	5.320s	417.401us	1	1	100.00
V2	tl_d_partial_access	rom_ctrl_csr_hw_reset	6.770s	131.319us	1	1	100.00
		rom_ctrl_csr_rw	6.100s	173.245us	1	1	100.00
		rom_ctrl_csr_aliasing	4.810s	558.020us	1	1	100.00
		rom_ctrl_same_csr_outstanding	5.320s	417.401us	1	1	100.00
V2		TOTAL			6	6	100.00
V2S	corrupt_sig_fatal_chk	rom_ctrl_corrupt_sig_fatal_chk	13.120s	354.382us	0	1	0.00
V2S	passthru_mem_tl_intg_err	rom_ctrl_passthru_mem_tl_intg_err	21.280s	5.044ms	1	1	100.00
V2S	tl_intg_err	rom_ctrl_sec_cm	2.926m	545.694us	1	1	100.00
		rom_ctrl_tl_intg_err	24.860s	384.653us	1	1	100.00
V2S	prim_fsm_check	rom_ctrl_sec_cm	2.926m	545.694us	1	1	100.00
V2S	prim_count_check	rom_ctrl_sec_cm	2.926m	545.694us	1	1	100.00
V2S	sec_cm_checker_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	13.120s	354.382us	0	1	0.00
V2S	sec_cm_checker_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	13.120s	354.382us	0	1	0.00
V2S	sec_cm_checker_fsm_local_esc	rom_ctrl_corrupt_sig_fatal_chk	13.120s	354.382us	0	1	0.00
V2S	sec_cm_compare_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	13.120s	354.382us	0	1	0.00
V2S	sec_cm_compare_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	13.120s	354.382us	0	1	0.00
V2S	sec_cm_compare_ctr_redun	rom_ctrl_sec_cm	2.926m	545.694us	1	1	100.00
V2S	sec_cm_fsm_sparse	rom_ctrl_sec_cm	2.926m	545.694us	1	1	100.00
V2S	sec_cm_mem_scramble	rom_ctrl_smoke	5.010s	238.548us	1	1	100.00
V2S	sec_cm_mem_digest	rom_ctrl_smoke	5.010s	238.548us	1	1	100.00
V2S	sec_cm_intersig_mubi	rom_ctrl_smoke	5.010s	238.548us	1	1	100.00
V2S	sec_cm_bus_integrity	rom_ctrl_tl_intg_err	24.860s	384.653us	1	1	100.00
V2S	sec_cm_bus_local_esc	rom_ctrl_corrupt_sig_fatal_chk	13.120s	354.382us	0	1	0.00
		rom_ctrl_kmac_err_chk	10.340s	397.154us	1	1	100.00
V2S	sec_cm_mux_mubi	rom_ctrl_corrupt_sig_fatal_chk	13.120s	354.382us	0	1	0.00
V2S	sec_cm_mux_consistency	rom_ctrl_corrupt_sig_fatal_chk	13.120s	354.382us	0	1	0.00
V2S	sec_cm_ctrl_redun	rom_ctrl_corrupt_sig_fatal_chk	13.120s	354.382us	0	1	0.00
V2S	sec_cm_ctrl_mem_integrity	rom_ctrl_passthru_mem_tl_intg_err	21.280s	5.044ms	1	1	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	rom_ctrl_sec_cm	2.926m	545.694us	1	1	100.00
V2S		TOTAL			3	4	75.00
V3	stress_all_with_rand_reset	rom_ctrl_stress_all_with_rand_reset	1.237m	10.187ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			18	19	94.74

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:695) virtual_sequencer [rom_ctrl_corrupt_sig_fatal_chk_vseq] expect alert:fatal to fire has 1 failures:
  • Test rom_ctrl_corrupt_sig_fatal_chk has 1 failures.

    • 0.rom_ctrl_corrupt_sig_fatal_chk.31599356264748838280628617871069441657645364895377324603957079945872714789697
      Line 73, in log /nightly/runs/scratch/master/rom_ctrl_32kB-sim-vcs/0.rom_ctrl_corrupt_sig_fatal_chk/latest/run.log

        UVM_ERROR @ 354381952 ps: (cip_base_vseq.sv:695) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.rom_ctrl_corrupt_sig_fatal_chk_vseq] expect alert:fatal to fire
        UVM_INFO @ 354381952 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---