RV_DM/USE_JTAG_INTERFACE Simulation Results

Wednesday May 07 2025 18:36:24 UTC

GitHub Revision: 3add6b6

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke rv_dm_smoke 4.710s 2.152ms 1 1 100.00
V1 jtag_dtm_csr_hw_reset rv_dm_jtag_dtm_csr_hw_reset 3.110s 785.904us 1 1 100.00
V1 jtag_dtm_csr_rw rv_dm_jtag_dtm_csr_rw 1.950s 194.355us 1 1 100.00
V1 jtag_dtm_csr_bit_bash rv_dm_jtag_dtm_csr_bit_bash 1.205m 32.459ms 1 1 100.00
V1 jtag_dtm_csr_aliasing rv_dm_jtag_dtm_csr_aliasing 2.320s 450.916us 1 1 100.00
V1 jtag_dmi_csr_hw_reset rv_dm_jtag_dmi_csr_hw_reset 6.230s 2.856ms 1 1 100.00
V1 jtag_dmi_csr_rw rv_dm_jtag_dmi_csr_rw 3.340s 1.022ms 1 1 100.00
V1 jtag_dmi_csr_bit_bash rv_dm_jtag_dmi_csr_bit_bash 1.099m 32.494ms 1 1 100.00
V1 jtag_dmi_csr_aliasing rv_dm_jtag_dmi_csr_aliasing 53.570s 42.279ms 1 1 100.00
V1 jtag_dmi_cmderr_busy rv_dm_cmderr_busy 2.640s 484.315us 1 1 100.00
V1 jtag_dmi_cmderr_not_supported rv_dm_cmderr_not_supported 2.420s 672.848us 1 1 100.00
V1 cmderr_exception rv_dm_cmderr_exception 2.500s 449.544us 1 1 100.00
V1 mem_tl_access_resuming rv_dm_mem_tl_access_resuming 1.920s 164.956us 1 1 100.00
V1 mem_tl_access_halted rv_dm_mem_tl_access_halted 2.120s 218.207us 1 1 100.00
V1 cmderr_halt_resume rv_dm_cmderr_halt_resume 1.910s 1.107ms 1 1 100.00
V1 dataaddr_rw_access rv_dm_dataaddr_rw_access 2.010s 376.212us 1 1 100.00
V1 halt_resume rv_dm_halt_resume_whereto 1.970s 205.286us 1 1 100.00
V1 progbuf_busy rv_dm_cmderr_busy 2.640s 484.315us 1 1 100.00
V1 abstractcmd_status rv_dm_abstractcmd_status 1.860s 261.802us 1 1 100.00
V1 progbuf_read_write_execute rv_dm_progbuf_read_write_execute 2.000s 251.703us 1 1 100.00
V1 progbuf_exception rv_dm_cmderr_exception 2.500s 449.544us 1 1 100.00
V1 rom_read_access rv_dm_rom_read_access 1.740s 191.392us 1 1 100.00
V1 csr_hw_reset rv_dm_csr_hw_reset 4.560s 296.472us 1 1 100.00
V1 csr_rw rv_dm_csr_rw 2.500s 104.308us 1 1 100.00
V1 csr_bit_bash rv_dm_csr_bit_bash 1.006m 32.746ms 1 1 100.00
V1 csr_aliasing rv_dm_csr_aliasing 52.900s 9.175ms 1 1 100.00
V1 csr_mem_rw_with_rand_reset rv_dm_csr_mem_rw_with_rand_reset 2.270s 150.030us 0 1 0.00
V1 regwen_csr_and_corresponding_lockable_csr rv_dm_csr_aliasing 52.900s 9.175ms 1 1 100.00
rv_dm_csr_rw 2.500s 104.308us 1 1 100.00
V1 mem_walk rv_dm_mem_walk 1.710s 35.232us 1 1 100.00
V1 mem_partial_access rv_dm_mem_partial_access 1.950s 114.172us 1 1 100.00
V1 TOTAL 26 27 96.30
V2 idcode rv_dm_smoke 4.710s 2.152ms 1 1 100.00
V2 jtag_dtm_hard_reset rv_dm_jtag_dtm_hard_reset 2.320s 400.743us 1 1 100.00
V2 jtag_dtm_idle_hint rv_dm_jtag_dtm_idle_hint 1.910s 125.736us 1 1 100.00
V2 jtag_dmi_failed_op rv_dm_dmi_failed_op 1.920s 127.628us 1 1 100.00
V2 jtag_dmi_dm_inactive rv_dm_jtag_dmi_dm_inactive 2.850s 1.981ms 1 1 100.00
V2 sba rv_dm_sba_tl_access 11.980s 5.190ms 1 1 100.00
rv_dm_delayed_resp_sba_tl_access 1.640s 56.100us 0 1 0.00
V2 bad_sba rv_dm_bad_sba_tl_access 6.260s 7.445ms 1 1 100.00
V2 sba_autoincrement rv_dm_autoincr_sba_tl_access 1.810s 46.247us 0 1 0.00
V2 jtag_dmi_debug_disabled rv_dm_jtag_dmi_debug_disabled 1.660s 91.578us 1 1 100.00
V2 sba_debug_disabled rv_dm_sba_debug_disabled 2.880s 1.509ms 1 1 100.00
V2 ndmreset_req rv_dm_ndmreset_req 3.480s 627.604us 1 1 100.00
V2 hart_unavail rv_dm_hart_unavail 2.180s 389.915us 1 1 100.00
V2 tap_ctrl_transitions rv_dm_tap_fsm 9.850s 9.799ms 1 1 100.00
rv_dm_tap_fsm_rand_reset 1.830s 72.359us 0 1 0.00
V2 hartsel_warl rv_dm_hartsel_warl 1.880s 163.182us 1 1 100.00
V2 stress_all rv_dm_stress_all 3.380s 2.174ms 1 1 100.00
V2 alert_test rv_dm_alert_test 2.070s 95.721us 1 1 100.00
V2 tl_d_oob_addr_access rv_dm_tl_errors 1.620s 25.388us 0 1 0.00
V2 tl_d_illegal_access rv_dm_tl_errors 1.620s 25.388us 0 1 0.00
V2 tl_d_outstanding_access rv_dm_csr_aliasing 52.900s 9.175ms 1 1 100.00
rv_dm_csr_hw_reset 4.560s 296.472us 1 1 100.00
rv_dm_csr_rw 2.500s 104.308us 1 1 100.00
rv_dm_same_csr_outstanding 4.410s 560.013us 1 1 100.00
V2 tl_d_partial_access rv_dm_csr_aliasing 52.900s 9.175ms 1 1 100.00
rv_dm_csr_hw_reset 4.560s 296.472us 1 1 100.00
rv_dm_csr_rw 2.500s 104.308us 1 1 100.00
rv_dm_same_csr_outstanding 4.410s 560.013us 1 1 100.00
V2 TOTAL 15 19 78.95
V2S tl_intg_err rv_dm_sec_cm 2.140s 717.960us 1 1 100.00
rv_dm_tl_intg_err 11.890s 3.973ms 1 1 100.00
V2S sec_cm_bus_integrity rv_dm_tl_intg_err 11.890s 3.973ms 1 1 100.00
V2S sec_cm_lc_hw_debug_en_intersig_mubi rv_dm_sba_debug_disabled 2.880s 1.509ms 1 1 100.00
rv_dm_debug_disabled 1.940s 107.548us 1 1 100.00
V2S sec_cm_lc_dft_en_intersig_mubi rv_dm_sba_debug_disabled 2.880s 1.509ms 1 1 100.00
rv_dm_debug_disabled 1.940s 107.548us 1 1 100.00
V2S sec_cm_otp_dis_rv_dm_late_debug_intersig_mubi rv_dm_smoke 4.710s 2.152ms 1 1 100.00
V2S sec_cm_dm_en_ctrl_lc_gated rv_dm_buffered_enable 2.050s 157.605us 1 1 100.00
V2S sec_cm_sba_tl_lc_gate_fsm_sparse rv_dm_sparse_lc_gate_fsm 1.790s 143.877us 1 1 100.00
V2S sec_cm_mem_tl_lc_gate_fsm_sparse rv_dm_sparse_lc_gate_fsm 1.790s 143.877us 1 1 100.00
V2S sec_cm_exec_ctrl_mubi rv_dm_buffered_enable 2.050s 157.605us 1 1 100.00
V2S TOTAL 5 5 100.00
V3 stress_all_with_rand_reset rv_dm_stress_all_with_rand_reset 1.460s 22.738us 0 1 0.00
V3 TOTAL 0 1 0.00
Unmapped tests rv_dm_scanmode 1.720s 18.295us 1 1 100.00
TOTAL 47 53 88.68

Failure Buckets