RV_TIMER Simulation Results

Wednesday May 07 2025 18:36:24 UTC

GitHub Revision: 3add6b6

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	random	rv_timer_random	1.520s	26.516us	1	1	100.00
V1	csr_hw_reset	rv_timer_csr_hw_reset	1.420s	32.580us	1	1	100.00
V1	csr_rw	rv_timer_csr_rw	1.450s	15.820us	1	1	100.00
V1	csr_bit_bash	rv_timer_csr_bit_bash	1.970s	203.253us	1	1	100.00
V1	csr_aliasing	rv_timer_csr_aliasing	1.630s	139.147us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	rv_timer_csr_mem_rw_with_rand_reset	1.960s	112.236us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rv_timer_csr_rw	1.450s	15.820us	1	1	100.00
		rv_timer_csr_aliasing	1.630s	139.147us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	random_reset	rv_timer_random_reset	1.650s	382.695us	1	1	100.00
V2	disabled	rv_timer_disabled	2.070s	1.289ms	1	1	100.00
V2	cfg_update_on_fly	rv_timer_cfg_update_on_fly	4.022m	396.132ms	1	1	100.00
V2	no_interrupt_test	rv_timer_cfg_update_on_fly	4.022m	396.132ms	1	1	100.00
V2	stress	rv_timer_stress_all	3.600s	2.047ms	1	1	100.00
V2	alert_test	rv_timer_alert_test	1.460s	42.277us	1	1	100.00
V2	intr_test	rv_timer_intr_test	1.540s	10.514us	1	1	100.00
V2	tl_d_oob_addr_access	rv_timer_tl_errors	2.480s	166.255us	1	1	100.00
V2	tl_d_illegal_access	rv_timer_tl_errors	2.480s	166.255us	1	1	100.00
V2	tl_d_outstanding_access	rv_timer_csr_hw_reset	1.420s	32.580us	1	1	100.00
		rv_timer_csr_rw	1.450s	15.820us	1	1	100.00
		rv_timer_csr_aliasing	1.630s	139.147us	1	1	100.00
		rv_timer_same_csr_outstanding	1.490s	21.006us	1	1	100.00
V2	tl_d_partial_access	rv_timer_csr_hw_reset	1.420s	32.580us	1	1	100.00
		rv_timer_csr_rw	1.450s	15.820us	1	1	100.00
		rv_timer_csr_aliasing	1.630s	139.147us	1	1	100.00
		rv_timer_same_csr_outstanding	1.490s	21.006us	1	1	100.00
V2		TOTAL			8	8	100.00
V2S	tl_intg_err	rv_timer_sec_cm	1.570s	441.476us	1	1	100.00
		rv_timer_tl_intg_err	2.040s	368.109us	1	1	100.00
V2S	sec_cm_bus_integrity	rv_timer_tl_intg_err	2.040s	368.109us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	stress_all_with_rand_reset	rv_timer_stress_all_with_rand_reset	28.200s	8.185ms	1	1	100.00
V3		TOTAL			1	1	100.00
	Unmapped tests	rv_timer_min	1.550s	16.896us	1	1	100.00
		rv_timer_max	1.460s	11.199us	1	1	100.00
		TOTAL			19	19	100.00