SPI_DEVICE/1R1W Simulation Results

Wednesday May 07 2025 18:36:24 UTC

GitHub Revision: 3add6b6

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	1.524m	26.953ms	1	1	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	2.030s	23.593us	1	1	100.00
V1	csr_rw	spi_device_csr_rw	2.460s	253.567us	1	1	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	17.710s	1.234ms	1	1	100.00
V1	csr_aliasing	spi_device_csr_aliasing	16.560s	9.987ms	1	1	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	3.580s	425.705us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	2.460s	253.567us	1	1	100.00
		spi_device_csr_aliasing	16.560s	9.987ms	1	1	100.00
V1	mem_walk	spi_device_mem_walk	1.480s	38.205us	1	1	100.00
V1	mem_partial_access	spi_device_mem_partial_access	2.460s	109.122us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	csb_read	spi_device_csb_read	1.840s	23.906us	1	1	100.00
V2	mem_parity	spi_device_mem_parity	1.630s	2.615us	0	1	0.00
V2	mem_cfg	spi_device_ram_cfg	2.050s	3.437us	0	1	0.00
V2	tpm_read	spi_device_tpm_rw	1.830s	39.398us	1	1	100.00
V2	tpm_write	spi_device_tpm_rw	1.830s	39.398us	1	1	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	14.310s	29.399ms	1	1	100.00
		spi_device_tpm_sts_read	1.690s	32.604us	1	1	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	27.440s	9.381ms	1	1	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	22.420s	45.110ms	1	1	100.00
		spi_device_flash_all	21.920s	8.169ms	1	1	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	4.440s	767.447us	1	1	100.00
		spi_device_flash_all	21.920s	8.169ms	1	1	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	4.440s	767.447us	1	1	100.00
		spi_device_flash_all	21.920s	8.169ms	1	1	100.00
V2	cmd_info_slots	spi_device_flash_all	21.920s	8.169ms	1	1	100.00
V2	cmd_read_status	spi_device_intercept	3.790s	50.144us	1	1	100.00
		spi_device_flash_all	21.920s	8.169ms	1	1	100.00
V2	cmd_read_jedec	spi_device_intercept	3.790s	50.144us	1	1	100.00
		spi_device_flash_all	21.920s	8.169ms	1	1	100.00
V2	cmd_read_sfdp	spi_device_intercept	3.790s	50.144us	1	1	100.00
		spi_device_flash_all	21.920s	8.169ms	1	1	100.00
V2	cmd_fast_read	spi_device_intercept	3.790s	50.144us	1	1	100.00
		spi_device_flash_all	21.920s	8.169ms	1	1	100.00
V2	cmd_read_pipeline	spi_device_intercept	3.790s	50.144us	1	1	100.00
		spi_device_flash_all	21.920s	8.169ms	1	1	100.00
V2	flash_cmd_upload	spi_device_upload	2.580s	52.999us	1	1	100.00
V2	mailbox_command	spi_device_mailbox	12.290s	1.165ms	1	1	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	12.290s	1.165ms	1	1	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	12.290s	1.165ms	1	1	100.00
V2	cmd_read_buffer	spi_device_flash_mode	34.890s	3.599ms	1	1	100.00
		spi_device_read_buffer_direct	5.200s	599.049us	1	1	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	12.290s	1.165ms	1	1	100.00
		spi_device_flash_all	21.920s	8.169ms	1	1	100.00
V2	quad_spi	spi_device_flash_all	21.920s	8.169ms	1	1	100.00
V2	dual_spi	spi_device_flash_all	21.920s	8.169ms	1	1	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	4.610s	340.620us	1	1	100.00
V2	write_enable_disable	spi_device_cfg_cmd	4.610s	340.620us	1	1	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	1.524m	26.953ms	1	1	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	13.260s	3.958ms	1	1	100.00
V2	stress_all	spi_device_stress_all	3.833m	321.596ms	1	1	100.00
V2	alert_test	spi_device_alert_test	1.900s	13.068us	1	1	100.00
V2	intr_test	spi_device_intr_test	1.590s	16.595us	1	1	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	2.990s	180.460us	1	1	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	2.990s	180.460us	1	1	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	2.030s	23.593us	1	1	100.00
		spi_device_csr_rw	2.460s	253.567us	1	1	100.00
		spi_device_csr_aliasing	16.560s	9.987ms	1	1	100.00
		spi_device_same_csr_outstanding	2.530s	183.731us	1	1	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	2.030s	23.593us	1	1	100.00
		spi_device_csr_rw	2.460s	253.567us	1	1	100.00
		spi_device_csr_aliasing	16.560s	9.987ms	1	1	100.00
		spi_device_same_csr_outstanding	2.530s	183.731us	1	1	100.00
V2		TOTAL			20	22	90.91
V2S	tl_intg_err	spi_device_sec_cm	1.970s	245.284us	1	1	100.00
		spi_device_tl_intg_err	10.740s	583.049us	1	1	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	10.740s	583.049us	1	1	100.00
V2S		TOTAL			2	2	100.00
	Unmapped tests	spi_device_flash_mode_ignore_cmds	40.330s	9.215ms	1	1	100.00
		TOTAL			31	33	93.94

Failure Buckets

• UVM_ERROR (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[*]) has 1 failures:

  • Test spi_device_mem_parity has 1 failures.

    • 0.spi_device_mem_parity.56070601465953863836330381332795948409122232993237327525291209950373138921193
      Line 71, in log /nightly/runs/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_mem_parity/latest/run.log

        UVM_ERROR @   2240051 ps: (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[110])
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
        UVM_ERROR @   2240051 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
        UVM_ERROR @   2240051 ps: (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[1006])
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
      

• UVM_ERROR (spi_device_ram_cfg_vseq.sv:27) [spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (* [*] vs *xxxxxxx [xxxxxxxxxxxxxxxxxxxxxxxx]) has 1 failures:

  • Test spi_device_ram_cfg has 1 failures.

    • 0.spi_device_ram_cfg.33418738483099731282161717513795776241047593604207794406604142825149120961934
      Line 71, in log /nightly/runs/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_ram_cfg/latest/run.log

        UVM_ERROR @    787160 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x214420 [1000010100010000100000] vs 0xxxxxxx [xxxxxxxxxxxxxxxxxxxxxxxx])
        UVM_ERROR @    839160 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x67e67f [11001111110011001111111] vs 0xxxxxxx [xxxxxxxxxxxxxxxxxxxxxxxx])
        UVM_ERROR @    932160 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x67427 [1100111010000100111] vs 0xxxxxxx [xxxxxxxxxxxxxxxxxxxxxxxx])
        UVM_ERROR @    956160 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x4b0209 [10010110000001000001001] vs 0xxxxxxx [xxxxxxxxxxxxxxxxxxxxxxxx])
        UVM_ERROR @   1048160 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x5b2f27 [10110110010111100100111] vs 0xxxxxxx [xxxxxxxxxxxxxxxxxxxxxxxx])