SPI_DEVICE/2P Simulation Results

Wednesday May 07 2025 18:36:24 UTC

GitHub Revision: 3add6b6

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	1.730m	69.070ms	1	1	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	1.970s	313.471us	1	1	100.00
V1	csr_rw	spi_device_csr_rw	3.010s	97.169us	1	1	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	19.190s	3.694ms	1	1	100.00
V1	csr_aliasing	spi_device_csr_aliasing	11.760s	913.041us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	2.430s	46.971us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	3.010s	97.169us	1	1	100.00
		spi_device_csr_aliasing	11.760s	913.041us	1	1	100.00
V1	mem_walk	spi_device_mem_walk	1.650s	31.941us	1	1	100.00
V1	mem_partial_access	spi_device_mem_partial_access	2.040s	55.889us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	csb_read	spi_device_csb_read	1.730s	28.524us	1	1	100.00
V2	mem_parity	spi_device_mem_parity	2.040s	184.680us	1	1	100.00
V2	mem_cfg	spi_device_ram_cfg	1.690s	42.433us	1	1	100.00
V2	tpm_read	spi_device_tpm_rw	2.870s	290.039us	1	1	100.00
V2	tpm_write	spi_device_tpm_rw	2.870s	290.039us	1	1	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	3.770s	658.043us	1	1	100.00
		spi_device_tpm_sts_read	1.830s	116.716us	1	1	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	7.740s	745.619us	1	1	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	12.900s	11.046ms	1	1	100.00
		spi_device_flash_all	6.560s	1.521ms	1	1	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	10.940s	34.000ms	1	1	100.00
		spi_device_flash_all	6.560s	1.521ms	1	1	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	10.940s	34.000ms	1	1	100.00
		spi_device_flash_all	6.560s	1.521ms	1	1	100.00
V2	cmd_info_slots	spi_device_flash_all	6.560s	1.521ms	1	1	100.00
V2	cmd_read_status	spi_device_intercept	6.120s	2.048ms	1	1	100.00
		spi_device_flash_all	6.560s	1.521ms	1	1	100.00
V2	cmd_read_jedec	spi_device_intercept	6.120s	2.048ms	1	1	100.00
		spi_device_flash_all	6.560s	1.521ms	1	1	100.00
V2	cmd_read_sfdp	spi_device_intercept	6.120s	2.048ms	1	1	100.00
		spi_device_flash_all	6.560s	1.521ms	1	1	100.00
V2	cmd_fast_read	spi_device_intercept	6.120s	2.048ms	1	1	100.00
		spi_device_flash_all	6.560s	1.521ms	1	1	100.00
V2	cmd_read_pipeline	spi_device_intercept	6.120s	2.048ms	1	1	100.00
		spi_device_flash_all	6.560s	1.521ms	1	1	100.00
V2	flash_cmd_upload	spi_device_upload	6.760s	7.183ms	1	1	100.00
V2	mailbox_command	spi_device_mailbox	26.240s	19.234ms	1	1	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	26.240s	19.234ms	1	1	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	26.240s	19.234ms	1	1	100.00
V2	cmd_read_buffer	spi_device_flash_mode	3.760s	1.087ms	1	1	100.00
		spi_device_read_buffer_direct	4.040s	239.393us	1	1	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	26.240s	19.234ms	1	1	100.00
		spi_device_flash_all	6.560s	1.521ms	1	1	100.00
V2	quad_spi	spi_device_flash_all	6.560s	1.521ms	1	1	100.00
V2	dual_spi	spi_device_flash_all	6.560s	1.521ms	1	1	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	3.420s	669.022us	1	1	100.00
V2	write_enable_disable	spi_device_cfg_cmd	3.420s	669.022us	1	1	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	1.730m	69.070ms	1	1	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	1.171m	16.656ms	1	1	100.00
V2	stress_all	spi_device_stress_all	2.120s	158.907us	1	1	100.00
V2	alert_test	spi_device_alert_test	1.570s	15.817us	1	1	100.00
V2	intr_test	spi_device_intr_test	1.830s	38.469us	1	1	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	3.970s	1.218ms	1	1	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	3.970s	1.218ms	1	1	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	1.970s	313.471us	1	1	100.00
		spi_device_csr_rw	3.010s	97.169us	1	1	100.00
		spi_device_csr_aliasing	11.760s	913.041us	1	1	100.00
		spi_device_same_csr_outstanding	2.470s	208.699us	1	1	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	1.970s	313.471us	1	1	100.00
		spi_device_csr_rw	3.010s	97.169us	1	1	100.00
		spi_device_csr_aliasing	11.760s	913.041us	1	1	100.00
		spi_device_same_csr_outstanding	2.470s	208.699us	1	1	100.00
V2		TOTAL			22	22	100.00
V2S	tl_intg_err	spi_device_sec_cm	1.860s	95.564us	1	1	100.00
		spi_device_tl_intg_err	6.480s	437.721us	1	1	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	6.480s	437.721us	1	1	100.00
V2S		TOTAL			2	2	100.00
	Unmapped tests	spi_device_flash_mode_ignore_cmds	1.480m	140.635ms	1	1	100.00
		TOTAL			33	33	100.00