SRAM_CTRL/MAIN Simulation Results

Wednesday May 07 2025 18:36:24 UTC

GitHub Revision: 3add6b6

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	19.740s	4.262ms	1	1	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	1.630s	14.364us	1	1	100.00
V1	csr_rw	sram_ctrl_csr_rw	1.650s	16.164us	1	1	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	2.310s	80.326us	1	1	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	1.630s	69.224us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	3.190s	1.058ms	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	1.650s	16.164us	1	1	100.00
		sram_ctrl_csr_aliasing	1.630s	69.224us	1	1	100.00
V1	mem_walk	sram_ctrl_mem_walk	3.085m	3.944ms	1	1	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	1.809m	4.490ms	1	1	100.00
V1		TOTAL			8	8	100.00
V2	multiple_keys	sram_ctrl_multiple_keys	5.455m	99.739ms	1	1	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	2.244m	15.325ms	1	1	100.00
V2	bijection	sram_ctrl_bijection	29.994m	110.434ms	1	1	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	6.575m	38.155ms	1	1	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	1.031m	16.118ms	1	1	100.00
V2	executable	sram_ctrl_executable	7.793m	6.323ms	1	1	100.00
V2	partial_access	sram_ctrl_partial_access	48.420s	1.325ms	1	1	100.00
		sram_ctrl_partial_access_b2b	4.682m	30.117ms	1	1	100.00
V2	max_throughput	sram_ctrl_max_throughput	15.940s	863.843us	1	1	100.00
		sram_ctrl_throughput_w_partial_write	5.230s	6.678ms	1	1	100.00
		sram_ctrl_throughput_w_readback	20.680s	858.278us	1	1	100.00
V2	regwen	sram_ctrl_regwen	11.182m	35.781ms	1	1	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	2.910s	356.694us	1	1	100.00
V2	stress_all	sram_ctrl_stress_all	1.041h	121.457ms	1	1	100.00
V2	alert_test	sram_ctrl_alert_test	1.620s	102.527us	1	1	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	3.890s	679.227us	1	1	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	3.890s	679.227us	1	1	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	1.630s	14.364us	1	1	100.00
		sram_ctrl_csr_rw	1.650s	16.164us	1	1	100.00
		sram_ctrl_csr_aliasing	1.630s	69.224us	1	1	100.00
		sram_ctrl_same_csr_outstanding	1.810s	20.216us	1	1	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	1.630s	14.364us	1	1	100.00
		sram_ctrl_csr_rw	1.650s	16.164us	1	1	100.00
		sram_ctrl_csr_aliasing	1.630s	69.224us	1	1	100.00
		sram_ctrl_same_csr_outstanding	1.810s	20.216us	1	1	100.00
V2		TOTAL			17	17	100.00
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	15.450s	15.431ms	1	1	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	1.600s	8.186us	0	1	0.00
		sram_ctrl_tl_intg_err	2.310s	683.034us	1	1	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	1.600s	8.186us	0	1	0.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	2.310s	683.034us	1	1	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	11.182m	35.781ms	1	1	100.00
V2S	sec_cm_readback_config_regwen	sram_ctrl_regwen	11.182m	35.781ms	1	1	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	1.650s	16.164us	1	1	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	7.793m	6.323ms	1	1	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	7.793m	6.323ms	1	1	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	7.793m	6.323ms	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	1.031m	16.118ms	1	1	100.00
V2S	sec_cm_prim_ram_ctrl_mubi	sram_ctrl_mubi_enc_err	5.560s	2.775ms	1	1	100.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	15.450s	15.431ms	1	1	100.00
V2S	sec_cm_mem_readback	sram_ctrl_readback_err	4.740s	1.402ms	1	1	100.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	19.740s	4.262ms	1	1	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	19.740s	4.262ms	1	1	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	7.793m	6.323ms	1	1	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	1.600s	8.186us	0	1	0.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	1.031m	16.118ms	1	1	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	1.600s	8.186us	0	1	0.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	1.600s	8.186us	0	1	0.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	19.740s	4.262ms	1	1	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	1.600s	8.186us	0	1	0.00
V2S		TOTAL			4	5	80.00
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	1.065m	955.939us	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			30	31	96.77

Failure Buckets

• UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: * has 1 failures:
  • Test sram_ctrl_sec_cm has 1 failures.

    • 0.sram_ctrl_sec_cm.36426791862048803971618300692120108226085173308900752986388902453720727900213
      Line 97, in log /nightly/runs/scratch/master/sram_ctrl_main-sim-vcs/0.sram_ctrl_sec_cm/latest/run.log

        UVM_ERROR @   8185836 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
        UVM_INFO @   8185836 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---