SRAM_CTRL/RET Simulation Results

Wednesday May 07 2025 18:36:24 UTC

GitHub Revision: 3add6b6

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	12.220s	747.940us	1	1	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	1.430s	44.695us	1	1	100.00
V1	csr_rw	sram_ctrl_csr_rw	1.540s	137.021us	1	1	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	2.380s	428.997us	1	1	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	1.760s	45.995us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	1.730s	111.883us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	1.540s	137.021us	1	1	100.00
		sram_ctrl_csr_aliasing	1.760s	45.995us	1	1	100.00
V1	mem_walk	sram_ctrl_mem_walk	8.600s	655.550us	1	1	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	4.740s	319.563us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	multiple_keys	sram_ctrl_multiple_keys	7.231m	6.146ms	1	1	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	5.146m	4.619ms	1	1	100.00
V2	bijection	sram_ctrl_bijection	43.510s	15.283ms	1	1	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	7.126m	12.710ms	1	1	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	7.270s	1.778ms	1	1	100.00
V2	executable	sram_ctrl_executable	2.005m	1.802ms	1	1	100.00
V2	partial_access	sram_ctrl_partial_access	25.560s	1.924ms	1	1	100.00
		sram_ctrl_partial_access_b2b	5.594m	72.016ms	1	1	100.00
V2	max_throughput	sram_ctrl_max_throughput	5.420s	100.596us	1	1	100.00
		sram_ctrl_throughput_w_partial_write	16.430s	102.639us	1	1	100.00
		sram_ctrl_throughput_w_readback	2.660s	183.633us	1	1	100.00
V2	regwen	sram_ctrl_regwen	5.342m	2.367ms	1	1	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	1.640s	71.537us	1	1	100.00
V2	stress_all	sram_ctrl_stress_all	26.975m	11.059ms	1	1	100.00
V2	alert_test	sram_ctrl_alert_test	1.500s	31.908us	1	1	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	2.780s	75.924us	1	1	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	2.780s	75.924us	1	1	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	1.430s	44.695us	1	1	100.00
		sram_ctrl_csr_rw	1.540s	137.021us	1	1	100.00
		sram_ctrl_csr_aliasing	1.760s	45.995us	1	1	100.00
		sram_ctrl_same_csr_outstanding	2.100s	13.924us	1	1	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	1.430s	44.695us	1	1	100.00
		sram_ctrl_csr_rw	1.540s	137.021us	1	1	100.00
		sram_ctrl_csr_aliasing	1.760s	45.995us	1	1	100.00
		sram_ctrl_same_csr_outstanding	2.100s	13.924us	1	1	100.00
V2		TOTAL			17	17	100.00
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	2.870s	914.307us	1	1	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	1.480s	1.239us	0	1	0.00
		sram_ctrl_tl_intg_err	2.840s	357.864us	1	1	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	1.480s	1.239us	0	1	0.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	2.840s	357.864us	1	1	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	5.342m	2.367ms	1	1	100.00
V2S	sec_cm_readback_config_regwen	sram_ctrl_regwen	5.342m	2.367ms	1	1	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	1.540s	137.021us	1	1	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	2.005m	1.802ms	1	1	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	2.005m	1.802ms	1	1	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	2.005m	1.802ms	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	7.270s	1.778ms	1	1	100.00
V2S	sec_cm_prim_ram_ctrl_mubi	sram_ctrl_mubi_enc_err	1.620s	101.341us	0	1	0.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	2.870s	914.307us	1	1	100.00
V2S	sec_cm_mem_readback	sram_ctrl_readback_err	1.760s	127.904us	1	1	100.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	12.220s	747.940us	1	1	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	12.220s	747.940us	1	1	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	2.005m	1.802ms	1	1	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	1.480s	1.239us	0	1	0.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	7.270s	1.778ms	1	1	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	1.480s	1.239us	0	1	0.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	1.480s	1.239us	0	1	0.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	12.220s	747.940us	1	1	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	1.480s	1.239us	0	1	0.00
V2S		TOTAL			3	5	60.00
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	45.760s	990.102us	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			29	31	93.55

Failure Buckets

• Offending 'reqfifo_rvalid' has 1 failures:

  • Test sram_ctrl_mubi_enc_err has 1 failures.

    • 0.sram_ctrl_mubi_enc_err.64758467965802554852451949188882652130128747530037779581092083773430365822677
      Line 99, in log /nightly/runs/scratch/master/sram_ctrl_ret-sim-vcs/0.sram_ctrl_mubi_enc_err/latest/run.log

            Offending 'reqfifo_rvalid'
        UVM_ERROR @ 101340822 ps: (tlul_adapter_sram.sv:640) [ASSERT FAILED] rvalidHighReqFifoEmpty
        UVM_INFO @ 101340822 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Offending '(!$isunknown(rdata_o))' has 1 failures:

  • Test sram_ctrl_sec_cm has 1 failures.

    • 0.sram_ctrl_sec_cm.103970228391847589616064631359114484319937215203228535384302880665351232974895
      Line 94, in log /nightly/runs/scratch/master/sram_ctrl_ret-sim-vcs/0.sram_ctrl_sec_cm/latest/run.log

            Offending '(!$isunknown(rdata_o))'
        UVM_ERROR @   1239147 ps: (prim_fifo_sync.sv:218) [ASSERT FAILED] DataKnown_A
        UVM_INFO @   1239147 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---