SYSRST_CTRL Simulation Results

Wednesday May 07 2025 18:36:24 UTC

GitHub Revision: 3add6b6

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke sysrst_ctrl_smoke 2.570s 2.139ms 1 1 100.00
V1 input_output_inverted sysrst_ctrl_in_out_inverted 2.390s 2.521ms 1 1 100.00
V1 combo_detect_ec_rst sysrst_ctrl_combo_detect_ec_rst 10.060s 2.410ms 1 1 100.00
V1 combo_detect_ec_rst_with_pre_cond sysrst_ctrl_combo_detect_ec_rst_with_pre_cond 4.540s 2.334ms 1 1 100.00
V1 csr_hw_reset sysrst_ctrl_csr_hw_reset 5.200s 6.048ms 1 1 100.00
V1 csr_rw sysrst_ctrl_csr_rw 3.420s 2.082ms 1 1 100.00
V1 csr_bit_bash sysrst_ctrl_csr_bit_bash 51.970s 61.562ms 1 1 100.00
V1 csr_aliasing sysrst_ctrl_csr_aliasing 5.070s 2.569ms 1 1 100.00
V1 csr_mem_rw_with_rand_reset sysrst_ctrl_csr_mem_rw_with_rand_reset 6.170s 2.084ms 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr sysrst_ctrl_csr_rw 3.420s 2.082ms 1 1 100.00
sysrst_ctrl_csr_aliasing 5.070s 2.569ms 1 1 100.00
V1 TOTAL 9 9 100.00
V2 combo_detect sysrst_ctrl_combo_detect 3.472m 107.307ms 1 1 100.00
V2 combo_detect_with_pre_cond sysrst_ctrl_combo_detect_with_pre_cond 31.330s 63.910ms 1 1 100.00
V2 auto_block_key_outputs sysrst_ctrl_auto_blk_key_output 2.240s 3.450ms 1 1 100.00
V2 keyboard_input_triggered_interrupt sysrst_ctrl_edge_detect 7.410s 3.858ms 1 1 100.00
V2 pin_output_keyboard_inversion_control sysrst_ctrl_pin_override_test 2.730s 2.523ms 1 1 100.00
V2 pin_input_value_accessibility sysrst_ctrl_pin_access_test 2.680s 2.230ms 1 1 100.00
V2 ec_power_on_reset sysrst_ctrl_ec_pwr_on_rst 9.670s 3.957ms 1 1 100.00
V2 flash_write_protect_output sysrst_ctrl_flash_wr_prot_out 3.980s 2.619ms 1 1 100.00
V2 ultra_low_power_test sysrst_ctrl_ultra_low_pwr 2.360s 11.843ms 1 1 100.00
V2 sysrst_ctrl_feature_disable sysrst_ctrl_feature_disable 29.650s 32.609ms 1 1 100.00
V2 stress_all sysrst_ctrl_stress_all 20.020s 9.129ms 1 1 100.00
V2 alert_test sysrst_ctrl_alert_test 8.600s 2.014ms 1 1 100.00
V2 intr_test sysrst_ctrl_intr_test 5.470s 2.016ms 1 1 100.00
V2 tl_d_oob_addr_access sysrst_ctrl_tl_errors 6.910s 2.089ms 1 1 100.00
V2 tl_d_illegal_access sysrst_ctrl_tl_errors 6.910s 2.089ms 1 1 100.00
V2 tl_d_outstanding_access sysrst_ctrl_csr_hw_reset 5.200s 6.048ms 1 1 100.00
sysrst_ctrl_csr_rw 3.420s 2.082ms 1 1 100.00
sysrst_ctrl_csr_aliasing 5.070s 2.569ms 1 1 100.00
sysrst_ctrl_same_csr_outstanding 6.280s 4.669ms 1 1 100.00
V2 tl_d_partial_access sysrst_ctrl_csr_hw_reset 5.200s 6.048ms 1 1 100.00
sysrst_ctrl_csr_rw 3.420s 2.082ms 1 1 100.00
sysrst_ctrl_csr_aliasing 5.070s 2.569ms 1 1 100.00
sysrst_ctrl_same_csr_outstanding 6.280s 4.669ms 1 1 100.00
V2 TOTAL 15 15 100.00
V2S tl_intg_err sysrst_ctrl_sec_cm 1.316m 42.011ms 1 1 100.00
sysrst_ctrl_tl_intg_err 44.660s 22.188ms 1 1 100.00
V2S sec_cm_bus_integrity sysrst_ctrl_tl_intg_err 44.660s 22.188ms 1 1 100.00
V2S TOTAL 2 2 100.00
V3 stress_all_with_rand_reset sysrst_ctrl_stress_all_with_rand_reset 7.020s 5.356ms 1 1 100.00
V3 TOTAL 1 1 100.00
TOTAL 27 27 100.00