UART Simulation Results

Wednesday May 07 2025 18:36:24 UTC

GitHub Revision: 3add6b6

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	uart_smoke	2.780s	959.510us	1	1	100.00
V1	csr_hw_reset	uart_csr_hw_reset	1.500s	11.651us	1	1	100.00
V1	csr_rw	uart_csr_rw	1.480s	19.049us	1	1	100.00
V1	csr_bit_bash	uart_csr_bit_bash	2.480s	209.484us	1	1	100.00
V1	csr_aliasing	uart_csr_aliasing	1.490s	20.688us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	uart_csr_mem_rw_with_rand_reset	1.690s	23.515us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	uart_csr_rw	1.480s	19.049us	1	1	100.00
		uart_csr_aliasing	1.490s	20.688us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	base_random_seq	uart_tx_rx	53.980s	112.130ms	1	1	100.00
V2	parity	uart_smoke	2.780s	959.510us	1	1	100.00
		uart_tx_rx	53.980s	112.130ms	1	1	100.00
V2	parity_error	uart_intr	16.030s	12.173ms	1	1	100.00
		uart_rx_parity_err	26.530s	105.228ms	1	1	100.00
V2	watermark	uart_tx_rx	53.980s	112.130ms	1	1	100.00
		uart_intr	16.030s	12.173ms	1	1	100.00
V2	fifo_full	uart_fifo_full	16.190s	17.370ms	1	1	100.00
V2	fifo_overflow	uart_fifo_overflow	11.300s	8.460ms	1	1	100.00
V2	fifo_reset	uart_fifo_reset	43.660s	41.698ms	1	1	100.00
V2	rx_frame_err	uart_intr	16.030s	12.173ms	1	1	100.00
V2	rx_break_err	uart_intr	16.030s	12.173ms	1	1	100.00
V2	rx_timeout	uart_intr	16.030s	12.173ms	1	1	100.00
V2	perf	uart_perf	2.851m	11.323ms	1	1	100.00
V2	sys_loopback	uart_loopback	3.730s	2.395ms	1	1	100.00
V2	line_loopback	uart_loopback	3.730s	2.395ms	1	1	100.00
V2	rx_noise_filter	uart_noise_filter	1.048m	101.685ms	1	1	100.00
V2	rx_start_bit_filter	uart_rx_start_bit_filter	2.650s	5.633ms	1	1	100.00
V2	tx_overide	uart_tx_ovrd	10.460s	7.384ms	1	1	100.00
V2	rx_oversample	uart_rx_oversample	29.750s	5.700ms	1	1	100.00
V2	long_b2b_transfer	uart_long_xfer_wo_dly	1.573m	122.287ms	1	1	100.00
V2	stress_all	uart_stress_all	3.330m	352.525ms	1	1	100.00
V2	alert_test	uart_alert_test	1.470s	12.296us	1	1	100.00
V2	intr_test	uart_intr_test	1.530s	32.773us	1	1	100.00
V2	tl_d_oob_addr_access	uart_tl_errors	2.130s	53.902us	1	1	100.00
V2	tl_d_illegal_access	uart_tl_errors	2.130s	53.902us	1	1	100.00
V2	tl_d_outstanding_access	uart_csr_hw_reset	1.500s	11.651us	1	1	100.00
		uart_csr_rw	1.480s	19.049us	1	1	100.00
		uart_csr_aliasing	1.490s	20.688us	1	1	100.00
		uart_same_csr_outstanding	1.480s	84.847us	1	1	100.00
V2	tl_d_partial_access	uart_csr_hw_reset	1.500s	11.651us	1	1	100.00
		uart_csr_rw	1.480s	19.049us	1	1	100.00
		uart_csr_aliasing	1.490s	20.688us	1	1	100.00
		uart_same_csr_outstanding	1.480s	84.847us	1	1	100.00
V2		TOTAL			18	18	100.00
V2S	tl_intg_err	uart_sec_cm	1.720s	77.467us	1	1	100.00
		uart_tl_intg_err	2.030s	96.061us	1	1	100.00
V2S	sec_cm_bus_integrity	uart_tl_intg_err	2.030s	96.061us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	stress_all_with_rand_reset	uart_stress_all_with_rand_reset	38.970s	12.687ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			27	27	100.00