CHIP Simulation Results

Wednesday May 07 2025 18:36:24 UTC

GitHub Revision: `3add6b6`

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	chip_sw_example_tests	chip_sw_example_flash	1.763m	2.129ms	1	1	100.00
		chip_sw_example_rom	1.078m	2.662ms	1	1	100.00
		chip_sw_example_manufacturer	2.527m	2.946ms	1	1	100.00
		chip_sw_example_concurrency	2.868m	3.248ms	1	1	100.00
V1	csr_hw_reset	chip_csr_hw_reset	2.219m	4.905ms	1	1	100.00
V1	csr_rw	chip_csr_rw	2.631m	4.325ms	1	1	100.00
V1	csr_bit_bash	chip_csr_bit_bash	2.167m	3.447ms	1	1	100.00
V1	csr_aliasing	chip_csr_aliasing	1.046h	38.470ms	1	1	100.00
V1	csr_mem_rw_with_rand_reset	chip_csr_mem_rw_with_rand_reset	8.959m	10.313ms	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	chip_csr_aliasing	1.046h	38.470ms	1	1	100.00
		chip_csr_rw	2.631m	4.325ms	1	1	100.00
V1	xbar_smoke	xbar_smoke	5.960s	156.810us	1	1	100.00
V1	chip_sw_gpio_out	chip_sw_gpio	4.828m	3.944ms	1	1	100.00
V1	chip_sw_gpio_in	chip_sw_gpio	4.828m	3.944ms	1	1	100.00
V1	chip_sw_gpio_irq	chip_sw_gpio	4.828m	3.944ms	1	1	100.00
V1	chip_sw_uart_tx_rx	chip_sw_uart_tx_rx	5.499m	4.752ms	1	1	100.00
V1	chip_sw_uart_rx_overflow	chip_sw_uart_tx_rx	5.499m	4.752ms	1	1	100.00
		chip_sw_uart_tx_rx_idx1	5.756m	3.553ms	1	1	100.00
		chip_sw_uart_tx_rx_idx2	5.369m	4.560ms	1	1	100.00
		chip_sw_uart_tx_rx_idx3	4.962m	4.042ms	1	1	100.00
V1	chip_sw_uart_baud_rate	chip_sw_uart_rand_baudrate	28.301m	12.798ms	1	1	100.00
V1	chip_sw_uart_tx_rx_alt_clk_freq	chip_sw_uart_tx_rx_alt_clk_freq	18.038m	8.165ms	1	1	100.00
		chip_sw_uart_tx_rx_alt_clk_freq_low_speed	9.918m	8.506ms	1	1	100.00
V1		TOTAL			18	18	100.00
V2	chip_pin_mux	chip_padctrl_attributes	2.669m	5.537ms	1	1	100.00
V2	chip_padctrl_attributes	chip_padctrl_attributes	2.669m	5.537ms	1	1	100.00
V2	chip_sw_sleep_pin_mio_dio_val	chip_sw_sleep_pin_mio_dio_val	3.199m	2.827ms	1	1	100.00
V2	chip_sw_sleep_pin_wake	chip_sw_sleep_pin_wake	4.251m	6.118ms	1	1	100.00
V2	chip_sw_sleep_pin_retention	chip_sw_sleep_pin_retention	2.872m	3.243ms	1	1	100.00
V2	chip_sw_tap_strap_sampling	chip_tap_straps_dev	1.884m	3.348ms	1	1	100.00
		chip_tap_straps_testunlock0	7.622m	8.175ms	1	1	100.00
		chip_tap_straps_rma	3.405m	4.087ms	1	1	100.00
		chip_tap_straps_prod	6.614m	7.530ms	1	1	100.00
V2	chip_sw_pattgen_ios	chip_sw_pattgen_ios	2.440m	3.089ms	1	1	100.00
V2	chip_sw_sleep_pwm_pulses	chip_sw_sleep_pwm_pulses	13.348m	9.356ms	1	1	100.00
V2	chip_sw_data_integrity	chip_sw_data_integrity_escalation	6.247m	6.172ms	1	1	100.00
V2	chip_sw_instruction_integrity	chip_sw_data_integrity_escalation	6.247m	6.172ms	1	1	100.00
V2	chip_sw_ast_clk_outputs	chip_sw_ast_clk_outputs	10.228m	7.657ms	1	1	100.00
V2	chip_sw_ast_clk_rst_inputs	chip_sw_ast_clk_rst_inputs	27.659m	20.687ms	0	1	0.00
V2	chip_sw_ast_sys_clk_jitter	chip_sw_flash_ctrl_ops_jitter_en	5.506m	4.208ms	1	1	100.00
		chip_sw_flash_ctrl_access_jitter_en	9.474m	5.731ms	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	53.288m	18.708ms	1	1	100.00
		chip_sw_aes_enc_jitter_en	3.118m	3.067ms	1	1	100.00
		chip_sw_edn_entropy_reqs_jitter	12.617m	6.948ms	1	1	100.00
		chip_sw_hmac_enc_jitter_en	2.350m	3.165ms	1	1	100.00
		chip_sw_keymgr_key_derivation_jitter_en	11.138m	7.894ms	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en	3.308m	3.419ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	5.346m	4.980ms	1	1	100.00
		chip_sw_clkmgr_jitter	2.859m	3.362ms	1	1	100.00
V2	chip_sw_ast_usb_clk_calib	chip_sw_usb_ast_clk_calib	2.622m	2.521ms	1	1	100.00
V2	chip_sw_sensor_ctrl_ast_alerts	chip_sw_sensor_ctrl_alert	7.769m	8.160ms	1	1	100.00
		chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	5.083m	5.355ms	1	1	100.00
V2	chip_sw_sensor_ctrl_ast_status	chip_sw_sensor_ctrl_status	2.548m	2.581ms	1	1	100.00
V2	chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	5.083m	5.355ms	1	1	100.00
V2	chip_sw_smoketest	chip_sw_flash_scrambling_smoketest	2.099m	2.896ms	1	1	100.00
		chip_sw_aes_smoketest	2.902m	2.996ms	1	1	100.00
		chip_sw_aon_timer_smoketest	3.329m	2.987ms	1	1	100.00
		chip_sw_clkmgr_smoketest	1.849m	3.271ms	1	1	100.00
		chip_sw_csrng_smoketest	3.096m	3.216ms	1	1	100.00
		chip_sw_entropy_src_smoketest	4.566m	3.771ms	1	1	100.00
		chip_sw_gpio_smoketest	3.391m	3.147ms	1	1	100.00
		chip_sw_hmac_smoketest	2.943m	3.655ms	1	1	100.00
		chip_sw_kmac_smoketest	3.160m	3.044ms	1	1	100.00
		chip_sw_otbn_smoketest	12.606m	7.850ms	1	1	100.00
		chip_sw_pwrmgr_smoketest	4.404m	5.531ms	1	1	100.00
		chip_sw_pwrmgr_usbdev_smoketest	4.523m	6.147ms	1	1	100.00
		chip_sw_rv_plic_smoketest	1.593m	2.379ms	1	1	100.00
		chip_sw_rv_timer_smoketest	2.159m	3.351ms	1	1	100.00
		chip_sw_rstmgr_smoketest	2.241m	2.810ms	1	1	100.00
		chip_sw_sram_ctrl_smoketest	1.818m	2.368ms	1	1	100.00
		chip_sw_uart_smoketest	1.924m	2.515ms	1	1	100.00
V2	chip_sw_otp_smoketest	chip_sw_otp_ctrl_smoketest	1.993m	3.107ms	1	1	100.00
V2	chip_sw_rom_functests	rom_keymgr_functest	5.112m	5.217ms	1	1	100.00
V2	chip_sw_boot	chip_sw_uart_tx_rx_bootstrap	1.933h	59.992ms	1	1	100.00
V2	chip_sw_secure_boot	rom_e2e_smoke	35.896m	15.025ms	1	1	100.00
V2	chip_sw_rom_raw_unlock	rom_raw_unlock	13.757s		0	1	0.00
V2	chip_sw_power_idle_load	chip_sw_power_idle_load	2.955m	3.034ms	0	1	0.00
V2	chip_sw_power_sleep_load	chip_sw_power_sleep_load	2.656m	3.090ms	0	1	0.00
V2	chip_sw_exit_test_unlocked_bootstrap	chip_sw_exit_test_unlocked_bootstrap	1.817h	53.713ms	1	1	100.00
V2	chip_sw_inject_scramble_seed	chip_sw_inject_scramble_seed	1.819h	56.302ms	1	1	100.00
V2	tl_d_oob_addr_access	chip_tl_errors	55.580s	2.626ms	0	1	0.00
V2	tl_d_illegal_access	chip_tl_errors	55.580s	2.626ms	0	1	0.00
V2	tl_d_outstanding_access	chip_csr_aliasing	1.046h	38.470ms	1	1	100.00
		chip_same_csr_outstanding	18.563m	16.465ms	1	1	100.00
		chip_csr_hw_reset	2.219m	4.905ms	1	1	100.00
		chip_csr_rw	2.631m	4.325ms	1	1	100.00
V2	tl_d_partial_access	chip_csr_aliasing	1.046h	38.470ms	1	1	100.00
		chip_same_csr_outstanding	18.563m	16.465ms	1	1	100.00
		chip_csr_hw_reset	2.219m	4.905ms	1	1	100.00
		chip_csr_rw	2.631m	4.325ms	1	1	100.00
V2	xbar_base_random_sequence	xbar_random	43.830s	2.192ms	1	1	100.00
V2	xbar_random_delay	xbar_smoke_zero_delays	5.400s	53.616us	1	1	100.00
		xbar_smoke_large_delays	51.150s	8.510ms	1	1	100.00
		xbar_smoke_slow_rsp	30.710s	3.304ms	1	1	100.00
		xbar_random_zero_delays	16.880s	364.134us	1	1	100.00
		xbar_random_large_delays	1.744m	16.794ms	1	1	100.00
		xbar_random_slow_rsp	4.106m	28.631ms	1	1	100.00
V2	xbar_unmapped_address	xbar_unmapped_addr	20.690s	306.039us	1	1	100.00
		xbar_error_and_unmapped_addr	32.030s	1.341ms	1	1	100.00
V2	xbar_error_cases	xbar_error_random	14.280s	529.241us	1	1	100.00
		xbar_error_and_unmapped_addr	32.030s	1.341ms	1	1	100.00
V2	xbar_all_access_same_device	xbar_access_same_device	40.980s	1.849ms	1	1	100.00
		xbar_access_same_device_slow_rsp	26.110s	2.878ms	1	1	100.00
V2	xbar_all_hosts_use_same_source_id	xbar_same_source	15.550s	339.753us	1	1	100.00
V2	xbar_stress_all	xbar_stress_all	4.649m	15.392ms	1	1	100.00
		xbar_stress_all_with_error	2.142m	3.167ms	1	1	100.00
V2	xbar_stress_with_reset	xbar_stress_all_with_rand_reset	3.264m	766.964us	1	1	100.00
		xbar_stress_all_with_reset_error	11.210s	7.562us	1	1	100.00
V2	rom_e2e_smoke	rom_e2e_smoke	35.896m	15.025ms	1	1	100.00
V2	rom_e2e_shutdown_output	rom_e2e_shutdown_output	31.104m	24.890ms	1	1	100.00
V2	rom_e2e_shutdown_exception_c	rom_e2e_shutdown_exception_c	35.711m	15.664ms	1	1	100.00
V2	rom_e2e_boot_policy_valid	rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0	18.869s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_dev	15.537s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod	15.712s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod_end	12.640s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_rma	18.253s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0	13.795s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_dev	12.192s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod	12.680s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod_end	12.329s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_rma	13.043s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0	13.028s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_dev	12.773s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod	12.291s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod_end	14.544s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_rma	11.873s		0	1	0.00
V2	rom_e2e_sigverify_always	rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0	14.325s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_dev	12.176s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod	13.524s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod_end	13.191s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_rma	12.655s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0	12.714s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_dev	12.113s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod	12.856s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod_end	12.679s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_rma	12.705s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0	13.187s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_dev	13.719s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod	13.220s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod_end	12.472s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_rma	12.749s		0	1	0.00
V2	rom_e2e_asm_init	rom_e2e_asm_init_test_unlocked0	12.288s		0	1	0.00
		rom_e2e_asm_init_dev	12.622s		0	1	0.00
		rom_e2e_asm_init_prod	13.918s		0	1	0.00
		rom_e2e_asm_init_prod_end	13.897s		0	1	0.00
		rom_e2e_asm_init_rma	13.739s		0	1	0.00
V2	rom_e2e_keymgr_init	rom_e2e_keymgr_init_rom_ext_meas	34.406m	14.388ms	1	1	100.00
		rom_e2e_keymgr_init_rom_ext_no_meas	34.802m	14.949ms	1	1	100.00
		rom_e2e_keymgr_init_rom_ext_invalid_meas	34.049m	14.828ms	1	1	100.00
V2	rom_e2e_static_critical	rom_e2e_static_critical	35.140m	16.155ms	1	1	100.00
V2	chip_sw_adc_ctrl_debug_cable_irq	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	45.403m	34.842ms	0	1	0.00
V2	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	45.403m	34.842ms	0	1	0.00
V2	chip_sw_aes_enc	chip_sw_aes_enc	2.785m	3.021ms	1	1	100.00
		chip_sw_aes_enc_jitter_en	3.118m	3.067ms	1	1	100.00
V2	chip_sw_aes_entropy	chip_sw_aes_entropy	2.160m	2.901ms	1	1	100.00
V2	chip_sw_aes_idle	chip_sw_aes_idle	2.212m	2.848ms	1	1	100.00
V2	chip_sw_aes_sideload	chip_sw_keymgr_sideload_aes	15.236m	9.314ms	1	1	100.00
V2	chip_sw_alert_handler_alerts	chip_sw_alert_test	3.412m	3.523ms	0	1	0.00
V2	chip_sw_alert_handler_escalations	chip_sw_alert_handler_escalation	4.679m	4.605ms	1	1	100.00
V2	chip_sw_all_escalation_resets	chip_sw_all_escalation_resets	5.722m	5.139ms	1	1	100.00
V2	chip_sw_alert_handler_irqs	chip_plic_all_irqs_0	9.262m	5.481ms	1	1	100.00
		chip_plic_all_irqs_10	4.535m	3.517ms	1	1	100.00
		chip_plic_all_irqs_20	5.857m	4.164ms	1	1	100.00
V2	chip_sw_alert_handler_entropy	chip_sw_alert_handler_entropy	2.638m	3.594ms	1	1	100.00
V2	chip_sw_alert_handler_crashdump	chip_sw_rstmgr_alert_info	17.103m	11.831ms	1	1	100.00
V2	chip_sw_alert_handler_ping_timeout	chip_sw_alert_handler_ping_timeout	3.004m	2.933ms	1	1	100.00
V2	chip_sw_alert_handler_lpg_sleep_mode_alerts	chip_sw_alert_handler_lpg_sleep_mode_alerts	2.304m	2.693ms	0	1	0.00
V2	chip_sw_alert_handler_lpg_sleep_mode_pings	chip_sw_alert_handler_lpg_sleep_mode_pings	9.680m	10.488ms	1	1	100.00
V2	chip_sw_alert_handler_lpg_clock_off	chip_sw_alert_handler_lpg_clkoff	12.925m	7.318ms	1	1	100.00
V2	chip_sw_alert_handler_lpg_reset_toggle	chip_sw_alert_handler_lpg_reset_toggle	16.856m	8.210ms	1	1	100.00
V2	chip_sw_alert_handler_ping_ok	chip_sw_alert_handler_ping_ok	13.862m	7.738ms	1	1	100.00
V2	chip_sw_alert_handler_reverse_ping_in_deep_sleep	chip_sw_alert_handler_reverse_ping_in_deep_sleep	1.839h	255.200ms	1	1	100.00
V2	chip_sw_aon_timer_wakeup_irq	chip_sw_aon_timer_irq	4.187m	4.243ms	1	1	100.00
V2	chip_sw_aon_timer_sleep_wakeup	chip_sw_pwrmgr_smoketest	4.404m	5.531ms	1	1	100.00
V2	chip_sw_aon_timer_wdog_bark_irq	chip_sw_aon_timer_irq	4.187m	4.243ms	1	1	100.00
V2	chip_sw_aon_timer_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	7.771m	7.636ms	1	1	100.00
V2	chip_sw_aon_timer_sleep_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	7.771m	7.636ms	1	1	100.00
V2	chip_sw_aon_timer_sleep_wdog_sleep_pause	chip_sw_aon_timer_sleep_wdog_sleep_pause	5.024m	6.376ms	1	1	100.00
V2	chip_sw_aon_timer_wdog_lc_escalate	chip_sw_aon_timer_wdog_lc_escalate	5.089m	5.132ms	1	1	100.00
V2	chip_sw_clkmgr_idle_trans	chip_sw_otbn_randomness	9.110m	5.861ms	1	1	100.00
		chip_sw_aes_idle	2.212m	2.848ms	1	1	100.00
		chip_sw_hmac_enc_idle	3.035m	3.021ms	1	1	100.00
		chip_sw_kmac_idle	2.107m	3.101ms	1	1	100.00
V2	chip_sw_clkmgr_off_trans	chip_sw_clkmgr_off_aes_trans	4.397m	5.316ms	1	1	100.00
		chip_sw_clkmgr_off_hmac_trans	4.409m	3.987ms	1	1	100.00
		chip_sw_clkmgr_off_kmac_trans	4.722m	4.671ms	1	1	100.00
		chip_sw_clkmgr_off_otbn_trans	4.701m	4.011ms	1	1	100.00
V2	chip_sw_clkmgr_off_peri	chip_sw_clkmgr_off_peri	9.220m	10.204ms	1	1	100.00
V2	chip_sw_clkmgr_div	chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	5.333m	3.690ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	5.812m	4.790ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	5.618m	4.046ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	5.323m	4.675ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	6.150m	4.244ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	5.986m	5.068ms	1	1	100.00
		chip_sw_ast_clk_outputs	10.228m	7.657ms	1	1	100.00
V2	chip_sw_clkmgr_external_clk_src_for_lc	chip_sw_clkmgr_external_clk_src_for_lc	3.500m	5.419ms	1	1	100.00
V2	chip_sw_clkmgr_external_clk_src_for_sw	chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	5.618m	4.046ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	5.323m	4.675ms	1	1	100.00
V2	chip_sw_clkmgr_jitter	chip_sw_flash_ctrl_ops_jitter_en	5.506m	4.208ms	1	1	100.00
		chip_sw_flash_ctrl_access_jitter_en	9.474m	5.731ms	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	53.288m	18.708ms	1	1	100.00
		chip_sw_aes_enc_jitter_en	3.118m	3.067ms	1	1	100.00
		chip_sw_edn_entropy_reqs_jitter	12.617m	6.948ms	1	1	100.00
		chip_sw_hmac_enc_jitter_en	2.350m	3.165ms	1	1	100.00
		chip_sw_keymgr_key_derivation_jitter_en	11.138m	7.894ms	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en	3.308m	3.419ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	5.346m	4.980ms	1	1	100.00
		chip_sw_clkmgr_jitter	2.859m	3.362ms	1	1	100.00
V2	chip_sw_clkmgr_extended_range	chip_sw_clkmgr_jitter_reduced_freq	2.263m	3.404ms	1	1	100.00
		chip_sw_flash_ctrl_ops_jitter_en_reduced_freq	6.237m	4.398ms	1	1	100.00
		chip_sw_flash_ctrl_access_jitter_en_reduced_freq	10.355m	7.157ms	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq	43.802m	24.203ms	1	1	100.00
		chip_sw_aes_enc_jitter_en_reduced_freq	2.880m	3.021ms	1	1	100.00
		chip_sw_hmac_enc_jitter_en_reduced_freq	2.519m	3.242ms	1	1	100.00
		chip_sw_keymgr_key_derivation_jitter_en_reduced_freq	16.011m	12.646ms	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en_reduced_freq	2.692m	3.398ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq	4.760m	4.046ms	1	1	100.00
		chip_sw_flash_init_reduced_freq	16.727m	27.124ms	1	1	100.00
		chip_sw_csrng_edn_concurrency_reduced_freq	27.713m	17.464ms	1	1	100.00
V2	chip_sw_clkmgr_deep_sleep_frequency	chip_sw_ast_clk_outputs	10.228m	7.657ms	1	1	100.00
V2	chip_sw_clkmgr_sleep_frequency	chip_sw_clkmgr_sleep_frequency	5.402m	4.565ms	1	1	100.00
V2	chip_sw_clkmgr_reset_frequency	chip_sw_clkmgr_reset_frequency	4.130m	3.933ms	1	1	100.00
V2	chip_sw_clkmgr_escalation_reset	chip_sw_all_escalation_resets	5.722m	5.139ms	1	1	100.00
V2	chip_sw_clkmgr_alert_handler_clock_enables	chip_sw_alert_handler_lpg_clkoff	12.925m	7.318ms	1	1	100.00
V2	chip_sw_csrng_edn_cmd	chip_sw_entropy_src_csrng	12.431m	6.589ms	1	1	100.00
V2	chip_sw_csrng_fuse_en_sw_app_read	chip_sw_csrng_fuse_en_sw_app_read_test	2.985m	2.870ms	0	1	0.00
V2	chip_sw_csrng_lc_hw_debug_en	chip_sw_csrng_lc_hw_debug_en_test	6.030m	7.207ms	1	1	100.00
V2	chip_sw_csrng_known_answer_tests	chip_sw_csrng_kat_test	2.074m	2.962ms	1	1	100.00
V2	chip_sw_edn_entropy_reqs	chip_sw_csrng_edn_concurrency	39.008m	15.761ms	1	1	100.00
		chip_sw_entropy_src_ast_rng_req	1.873m	2.607ms	1	1	100.00
		chip_sw_edn_entropy_reqs	12.111m	8.362ms	1	1	100.00
V2	chip_sw_entropy_src_ast_rng_req	chip_sw_entropy_src_ast_rng_req	1.873m	2.607ms	1	1	100.00
V2	chip_sw_entropy_src_csrng	chip_sw_entropy_src_csrng	12.431m	6.589ms	1	1	100.00
V2	chip_sw_entropy_src_known_answer_tests	chip_sw_entropy_src_kat_test	2.353m	2.850ms	1	1	100.00
V2	chip_sw_flash_init	chip_sw_flash_init	17.350m	17.068ms	1	1	100.00
V2	chip_sw_flash_host_access	chip_sw_flash_ctrl_access	9.780m	5.972ms	1	1	100.00
		chip_sw_flash_ctrl_access_jitter_en	9.474m	5.731ms	1	1	100.00
V2	chip_sw_flash_ctrl_ops	chip_sw_flash_ctrl_ops	5.200m	4.037ms	1	1	100.00
		chip_sw_flash_ctrl_ops_jitter_en	5.506m	4.208ms	1	1	100.00
V2	chip_sw_flash_rma_unlocked	chip_sw_flash_rma_unlocked	54.172m	44.672ms	1	1	100.00
V2	chip_sw_flash_scramble	chip_sw_flash_init	17.350m	17.068ms	1	1	100.00
V2	chip_sw_flash_idle_low_power	chip_sw_flash_ctrl_idle_low_power	3.033m	3.800ms	1	1	100.00
V2	chip_sw_flash_keymgr_seeds	chip_sw_keymgr_key_derivation	19.376m	10.401ms	1	1	100.00
V2	chip_sw_flash_lc_creator_seed_sw_rw_en	chip_sw_flash_ctrl_lc_rw_en	4.756m	3.914ms	1	1	100.00
V2	chip_sw_flash_creator_seed_wipe_on_rma	chip_sw_flash_rma_unlocked	54.172m	44.672ms	1	1	100.00
V2	chip_sw_flash_lc_owner_seed_sw_rw_en	chip_sw_flash_ctrl_lc_rw_en	4.756m	3.914ms	1	1	100.00
V2	chip_sw_flash_lc_iso_part_sw_rd_en	chip_sw_flash_ctrl_lc_rw_en	4.756m	3.914ms	1	1	100.00
V2	chip_sw_flash_lc_iso_part_sw_wr_en	chip_sw_flash_ctrl_lc_rw_en	4.756m	3.914ms	1	1	100.00
V2	chip_sw_flash_lc_seed_hw_rd_en	chip_sw_flash_ctrl_lc_rw_en	4.756m	3.914ms	1	1	100.00
V2	chip_sw_flash_lc_escalate_en	chip_sw_all_escalation_resets	5.722m	5.139ms	1	1	100.00
V2	chip_sw_flash_prim_tl_access	chip_prim_tl_access	2.070m	6.001ms	1	1	100.00
V2	chip_sw_flash_ctrl_clock_freqs	chip_sw_flash_ctrl_clock_freqs	8.636m	5.035ms	1	1	100.00
V2	chip_sw_flash_ctrl_escalation_reset	chip_sw_flash_crash_alert	6.412m	6.324ms	1	1	100.00
V2	chip_sw_flash_ctrl_write_clear	chip_sw_flash_crash_alert	6.412m	6.324ms	1	1	100.00
V2	chip_sw_hmac_enc	chip_sw_hmac_enc	2.874m	3.451ms	1	1	100.00
		chip_sw_hmac_enc_jitter_en	2.350m	3.165ms	1	1	100.00
V2	chip_sw_hmac_idle	chip_sw_hmac_enc_idle	3.035m	3.021ms	1	1	100.00
V2	chip_sw_hmac_all_configurations	chip_sw_hmac_oneshot	2.816m	3.198ms	1	1	100.00
V2	chip_sw_hmac_multistream_mode	chip_sw_hmac_multistream	14.692m	7.465ms	1	1	100.00
V2	chip_sw_i2c_host_tx_rx	chip_sw_i2c_host_tx_rx	5.481m	4.760ms	1	1	100.00
		chip_sw_i2c_host_tx_rx_idx1	7.094m	5.380ms	1	1	100.00
		chip_sw_i2c_host_tx_rx_idx2	5.214m	3.679ms	1	1	100.00
V2	chip_sw_i2c_device_tx_rx	chip_sw_i2c_device_tx_rx	4.352m	3.835ms	1	1	100.00
V2	chip_sw_keymgr_key_derivation	chip_sw_keymgr_key_derivation	19.376m	10.401ms	1	1	100.00
		chip_sw_keymgr_key_derivation_jitter_en	11.138m	7.894ms	1	1	100.00
V2	chip_sw_keymgr_sideload_kmac	chip_sw_keymgr_sideload_kmac	10.920m	6.817ms	1	1	100.00
V2	chip_sw_keymgr_sideload_aes	chip_sw_keymgr_sideload_aes	15.236m	9.314ms	1	1	100.00
V2	chip_sw_keymgr_sideload_otbn	chip_sw_keymgr_sideload_otbn	40.916m	15.625ms	1	1	100.00
V2	chip_sw_kmac_enc	chip_sw_kmac_mode_cshake	2.454m	2.887ms	1	1	100.00
		chip_sw_kmac_mode_kmac	3.407m	2.953ms	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en	3.308m	3.419ms	1	1	100.00
V2	chip_sw_kmac_app_keymgr	chip_sw_keymgr_key_derivation	19.376m	10.401ms	1	1	100.00
V2	chip_sw_kmac_app_lc	chip_sw_lc_ctrl_transition	11.050m	13.959ms	1	1	100.00
V2	chip_sw_kmac_app_rom	chip_sw_kmac_app_rom	2.516m	2.911ms	1	1	100.00
V2	chip_sw_kmac_entropy	chip_sw_kmac_entropy	8.685m	5.055ms	1	1	100.00
V2	chip_sw_kmac_idle	chip_sw_kmac_idle	2.107m	3.101ms	1	1	100.00
V2	chip_sw_lc_ctrl_alert_handler_escalation	chip_sw_alert_handler_escalation	4.679m	4.605ms	1	1	100.00
V2	chip_sw_lc_ctrl_jtag_access	chip_tap_straps_dev	1.884m	3.348ms	1	1	100.00
		chip_tap_straps_rma	3.405m	4.087ms	1	1	100.00
		chip_tap_straps_prod	6.614m	7.530ms	1	1	100.00
V2	chip_sw_lc_ctrl_otp_hw_cfg0	chip_sw_lc_ctrl_otp_hw_cfg0	2.938m	3.334ms	1	1	100.00
V2	chip_sw_lc_ctrl_init	chip_sw_lc_ctrl_transition	11.050m	13.959ms	1	1	100.00
V2	chip_sw_lc_ctrl_transitions	chip_sw_lc_ctrl_transition	11.050m	13.959ms	1	1	100.00
V2	chip_sw_lc_ctrl_kmac_req	chip_sw_lc_ctrl_transition	11.050m	13.959ms	1	1	100.00
V2	chip_sw_lc_ctrl_key_div	chip_sw_keymgr_key_derivation_prod	17.525m	9.290ms	1	1	100.00
V2	chip_sw_lc_ctrl_broadcast	chip_sw_flash_ctrl_lc_rw_en	4.756m	3.914ms	1	1	100.00
		chip_sw_flash_rma_unlocked	54.172m	44.672ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_test_unlocked0	3.347m	2.811ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_dev	8.483m	7.614ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_prod	9.426m	7.281ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_rma	8.516m	5.905ms	1	1	100.00
		chip_sw_lc_ctrl_transition	11.050m	13.959ms	1	1	100.00
		chip_sw_keymgr_key_derivation	19.376m	10.401ms	1	1	100.00
		chip_sw_rom_ctrl_integrity_check	5.259m	8.789ms	1	1	100.00
		chip_sw_sram_ctrl_execution_main	8.510m	6.677ms	1	1	100.00
		chip_prim_tl_access	2.070m	6.001ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_lc	3.500m	5.419ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	5.333m	3.690ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	5.812m	4.790ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	5.618m	4.046ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	5.323m	4.675ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	6.150m	4.244ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	5.986m	5.068ms	1	1	100.00
		chip_tap_straps_dev	1.884m	3.348ms	1	1	100.00
		chip_tap_straps_rma	3.405m	4.087ms	1	1	100.00
		chip_tap_straps_prod	6.614m	7.530ms	1	1	100.00
		chip_rv_dm_lc_disabled	5.898m	16.654ms	1	1	100.00
V2	chip_lc_scrap	chip_sw_lc_ctrl_rma_to_scrap	2.594m	3.283ms	1	1	100.00
		chip_sw_lc_ctrl_raw_to_scrap	1.713m	2.834ms	1	1	100.00
		chip_sw_lc_ctrl_test_locked0_to_scrap	1.357m	3.353ms	1	1	100.00
		chip_sw_lc_ctrl_rand_to_scrap	2.343m	3.705ms	1	1	100.00
V2	chip_lc_test_locked	chip_sw_lc_walkthrough_testunlocks	25.180m	28.199ms	1	1	100.00
		chip_rv_dm_lc_disabled	5.898m	16.654ms	1	1	100.00
V2	chip_sw_lc_walkthrough	chip_sw_lc_walkthrough_dev	59.730m	51.465ms	1	1	100.00
		chip_sw_lc_walkthrough_prod	1.041h	52.064ms	1	1	100.00
		chip_sw_lc_walkthrough_prodend	6.878m	7.418ms	1	1	100.00
		chip_sw_lc_walkthrough_rma	58.464m	46.868ms	1	1	100.00
		chip_sw_lc_walkthrough_testunlocks	25.180m	28.199ms	1	1	100.00
V2	chip_sw_lc_ctrl_volatile_raw_unlock	chip_sw_lc_ctrl_volatile_raw_unlock	1.143m	2.041ms	1	1	100.00
		chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz	1.286m	1.983ms	1	1	100.00
		rom_volatile_raw_unlock	20.170s		0	1	0.00
V2	chip_sw_otbn_op	chip_sw_otbn_ecdsa_op_irq	51.386m	16.939ms	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	53.288m	18.708ms	1	1	100.00
V2	chip_sw_otbn_rnd_entropy	chip_sw_otbn_randomness	9.110m	5.861ms	1	1	100.00
V2	chip_sw_otbn_urnd_entropy	chip_sw_otbn_randomness	9.110m	5.861ms	1	1	100.00
V2	chip_sw_otbn_idle	chip_sw_otbn_randomness	9.110m	5.861ms	1	1	100.00
V2	chip_sw_otbn_mem_scramble	chip_sw_otbn_mem_scramble	4.437m	3.514ms	1	1	100.00
V2	chip_otp_ctrl_init	chip_sw_lc_ctrl_transition	11.050m	13.959ms	1	1	100.00
V2	chip_sw_otp_ctrl_keys	chip_sw_flash_init	17.350m	17.068ms	1	1	100.00
		chip_sw_otbn_mem_scramble	4.437m	3.514ms	1	1	100.00
		chip_sw_keymgr_key_derivation	19.376m	10.401ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access	4.270m	4.769ms	1	1	100.00
		chip_sw_rv_core_ibex_icache_invalidate	2.128m	2.772ms	1	1	100.00
V2	chip_sw_otp_ctrl_entropy	chip_sw_flash_init	17.350m	17.068ms	1	1	100.00
		chip_sw_otbn_mem_scramble	4.437m	3.514ms	1	1	100.00
		chip_sw_keymgr_key_derivation	19.376m	10.401ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access	4.270m	4.769ms	1	1	100.00
		chip_sw_rv_core_ibex_icache_invalidate	2.128m	2.772ms	1	1	100.00
V2	chip_sw_otp_ctrl_program	chip_sw_lc_ctrl_transition	11.050m	13.959ms	1	1	100.00
V2	chip_sw_otp_ctrl_program_error	chip_sw_lc_ctrl_program_error	6.268m	5.011ms	1	1	100.00
V2	chip_sw_otp_ctrl_hw_cfg0	chip_sw_lc_ctrl_otp_hw_cfg0	2.938m	3.334ms	1	1	100.00
V2	chip_sw_otp_ctrl_lc_signals	chip_sw_otp_ctrl_lc_signals_test_unlocked0	3.347m	2.811ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_dev	8.483m	7.614ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_prod	9.426m	7.281ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_rma	8.516m	5.905ms	1	1	100.00
		chip_sw_lc_ctrl_transition	11.050m	13.959ms	1	1	100.00
		chip_prim_tl_access	2.070m	6.001ms	1	1	100.00
V2	chip_sw_otp_prim_tl_access	chip_prim_tl_access	2.070m	6.001ms	1	1	100.00
V2	chip_sw_otp_ctrl_dai_lock	chip_sw_otp_ctrl_dai_lock	16.944m	9.430ms	1	1	100.00
V2	chip_sw_pwrmgr_external_full_reset	chip_sw_pwrmgr_full_aon_reset	5.007m	8.205ms	1	1	100.00
V2	chip_sw_pwrmgr_random_sleep_all_wake_ups	chip_sw_pwrmgr_random_sleep_all_wake_ups	19.587m	28.974ms	1	1	100.00
V2	chip_sw_pwrmgr_normal_sleep_all_wake_ups	chip_sw_pwrmgr_normal_sleep_all_wake_ups	3.963m	7.475ms	1	1	100.00
V2	chip_sw_pwrmgr_deep_sleep_por_reset	chip_sw_pwrmgr_deep_sleep_por_reset	7.284m	9.834ms	1	1	100.00
V2	chip_sw_pwrmgr_normal_sleep_por_reset	chip_sw_pwrmgr_normal_sleep_por_reset	4.619m	5.703ms	1	1	100.00
V2	chip_sw_pwrmgr_deep_sleep_all_wake_ups	chip_sw_pwrmgr_deep_sleep_all_wake_ups	13.730m	25.367ms	1	1	100.00
V2	chip_sw_pwrmgr_deep_sleep_all_reset_reqs	chip_sw_pwrmgr_deep_sleep_all_reset_reqs	11.358m	12.730ms	1	1	100.00
		chip_sw_aon_timer_wdog_bite_reset	7.771m	7.636ms	1	1	100.00
V2	chip_sw_pwrmgr_normal_sleep_all_reset_reqs	chip_sw_pwrmgr_normal_sleep_all_reset_reqs	11.673m	9.269ms	1	1	100.00
V2	chip_sw_pwrmgr_wdog_reset	chip_sw_pwrmgr_wdog_reset	5.914m	4.724ms	1	1	100.00
V2	chip_sw_pwrmgr_aon_power_glitch_reset	chip_sw_pwrmgr_full_aon_reset	5.007m	8.205ms	1	1	100.00
V2	chip_sw_pwrmgr_main_power_glitch_reset	chip_sw_pwrmgr_main_power_glitch_reset	4.987m	4.095ms	1	1	100.00
V2	chip_sw_pwrmgr_random_sleep_power_glitch_reset	chip_sw_pwrmgr_random_sleep_power_glitch_reset	30.992m	39.807ms	1	1	100.00
V2	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	5.438m	6.560ms	1	1	100.00
V2	chip_sw_pwrmgr_sleep_power_glitch_reset	chip_sw_pwrmgr_sleep_power_glitch_reset	3.440m	4.368ms	1	1	100.00
V2	chip_sw_pwrmgr_random_sleep_all_reset_reqs	chip_sw_pwrmgr_random_sleep_all_reset_reqs	22.422m	26.489ms	1	1	100.00
V2	chip_sw_pwrmgr_sysrst_ctrl_reset	chip_sw_pwrmgr_sysrst_ctrl_reset	11.515m	7.465ms	1	1	100.00
		chip_sw_pwrmgr_all_reset_reqs	10.927m	8.485ms	1	1	100.00
V2	chip_sw_pwrmgr_b2b_sleep_reset_req	chip_sw_pwrmgr_b2b_sleep_reset_req	19.625m	25.603ms	1	1	100.00
V2	chip_sw_pwrmgr_sleep_disabled	chip_sw_pwrmgr_sleep_disabled	2.911m	3.900ms	1	1	100.00
V2	chip_sw_pwrmgr_escalation_reset	chip_sw_all_escalation_resets	5.722m	5.139ms	1	1	100.00
V2	chip_sw_rom_access	chip_sw_rom_ctrl_integrity_check	5.259m	8.789ms	1	1	100.00
V2	chip_sw_rom_ctrl_integrity_check	chip_sw_rom_ctrl_integrity_check	5.259m	8.789ms	1	1	100.00
V2	chip_sw_rstmgr_non_sys_reset_info	chip_sw_pwrmgr_all_reset_reqs	10.927m	8.485ms	1	1	100.00
		chip_sw_pwrmgr_random_sleep_all_reset_reqs	22.422m	26.489ms	1	1	100.00
		chip_sw_pwrmgr_wdog_reset	5.914m	4.724ms	1	1	100.00
		chip_sw_pwrmgr_smoketest	4.404m	5.531ms	1	1	100.00
V2	chip_sw_rstmgr_sys_reset_info	chip_rv_dm_ndm_reset_req	4.070m	3.543ms	1	1	100.00
V2	chip_sw_rstmgr_cpu_info	chip_sw_rstmgr_cpu_info	3.701m	4.179ms	0	1	0.00
V2	chip_sw_rstmgr_sw_req_reset	chip_sw_rstmgr_sw_req	3.376m	4.597ms	1	1	100.00
V2	chip_sw_rstmgr_alert_info	chip_sw_rstmgr_alert_info	17.103m	11.831ms	1	1	100.00
V2	chip_sw_rstmgr_sw_rst	chip_sw_rstmgr_sw_rst	2.016m	3.326ms	1	1	100.00
V2	chip_sw_rstmgr_escalation_reset	chip_sw_all_escalation_resets	5.722m	5.139ms	1	1	100.00
V2	chip_sw_rstmgr_alert_handler_reset_enables	chip_sw_alert_handler_lpg_reset_toggle	16.856m	8.210ms	1	1	100.00
V2	chip_sw_nmi_irq	chip_sw_rv_core_ibex_nmi_irq	8.508m	5.209ms	1	1	100.00
V2	chip_sw_rv_core_ibex_rnd	chip_sw_rv_core_ibex_rnd	7.940m	5.376ms	1	1	100.00
V2	chip_sw_rv_core_ibex_address_translation	chip_sw_rv_core_ibex_address_translation	3.003m	2.827ms	1	1	100.00
V2	chip_sw_rv_core_ibex_icache_scrambled_access	chip_sw_rv_core_ibex_icache_invalidate	2.128m	2.772ms	1	1	100.00
V2	chip_sw_rv_core_ibex_fault_dump	chip_sw_rstmgr_cpu_info	3.701m	4.179ms	0	1	0.00
V2	chip_sw_rv_core_ibex_double_fault	chip_sw_rstmgr_cpu_info	3.701m	4.179ms	0	1	0.00
V2	chip_jtag_csr_rw	chip_jtag_csr_rw	12.958m	12.305ms	1	1	100.00
V2	chip_jtag_mem_access	chip_jtag_mem_access	13.542m	13.527ms	1	1	100.00
V2	chip_rv_dm_ndm_reset_req	chip_rv_dm_ndm_reset_req	4.070m	3.543ms	1	1	100.00
V2	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	4.846m	3.639ms	1	1	100.00
V2	chip_rv_dm_access_after_wakeup	chip_sw_rv_dm_access_after_wakeup	4.617m	6.004ms	1	1	100.00
V2	chip_sw_rv_dm_jtag_tap_sel	chip_tap_straps_rma	3.405m	4.087ms	1	1	100.00
V2	chip_rv_dm_lc_disabled	chip_rv_dm_lc_disabled	5.898m	16.654ms	1	1	100.00
V2	chip_sw_plic_all_irqs	chip_plic_all_irqs_0	9.262m	5.481ms	1	1	100.00
		chip_plic_all_irqs_10	4.535m	3.517ms	1	1	100.00
		chip_plic_all_irqs_20	5.857m	4.164ms	1	1	100.00
V2	chip_sw_plic_sw_irq	chip_sw_plic_sw_irq	2.078m	2.328ms	1	1	100.00
V2	chip_sw_timer	chip_sw_rv_timer_irq	2.127m	3.179ms	1	1	100.00
V2	chip_sw_spi_device_flash_mode	rom_e2e_smoke	35.896m	15.025ms	1	1	100.00
V2	chip_sw_spi_device_pass_through	chip_sw_spi_device_pass_through	7.410m	6.128ms	1	1	100.00
V2	chip_sw_spi_device_pass_through_collision	chip_sw_spi_device_pass_through_collision	3.041m	3.816ms	0	1	0.00
V2	chip_sw_spi_device_tpm	chip_sw_spi_device_tpm	3.891m	3.870ms	1	1	100.00
V2	chip_sw_spi_host_tx_rx	chip_sw_spi_host_tx_rx	2.833m	2.672ms	1	1	100.00
V2	chip_sw_sram_scrambled_access	chip_sw_sram_ctrl_scrambled_access	4.270m	4.769ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	5.346m	4.980ms	1	1	100.00
V2	chip_sw_sleep_sram_ret_contents	chip_sw_sleep_sram_ret_contents_no_scramble	6.243m	7.233ms	1	1	100.00
		chip_sw_sleep_sram_ret_contents_scramble	6.178m	8.572ms	1	1	100.00
V2	chip_sw_sram_execution	chip_sw_sram_ctrl_execution_main	8.510m	6.677ms	1	1	100.00
V2	chip_sw_sram_lc_escalation	chip_sw_all_escalation_resets	5.722m	5.139ms	1	1	100.00
		chip_sw_data_integrity_escalation	6.247m	6.172ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_reset	chip_sw_pwrmgr_sysrst_ctrl_reset	11.515m	7.465ms	1	1	100.00
		chip_sw_sysrst_ctrl_reset	16.410m	22.280ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_inputs	chip_sw_sysrst_ctrl_inputs	1.892m	2.163ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_outputs	chip_sw_sysrst_ctrl_outputs	3.518m	3.622ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_in_irq	chip_sw_sysrst_ctrl_in_irq	4.757m	4.069ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_sleep_wakeup	chip_sw_sysrst_ctrl_reset	16.410m	22.280ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_sleep_reset	chip_sw_sysrst_ctrl_reset	16.410m	22.280ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_ec_rst_l	chip_sw_sysrst_ctrl_ec_rst_l	37.321m	20.836ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_flash_wp_l	chip_sw_sysrst_ctrl_ec_rst_l	37.321m	20.836ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_ulp_z3_wakeup	chip_sw_sysrst_ctrl_ulp_z3_wakeup	6.222m	7.099ms	1	1	100.00
		chip_sw_adc_ctrl_sleep_debug_cable_wakeup	45.403m	34.842ms	0	1	0.00
V2	chip_sw_usbdev_vbus	chip_sw_usbdev_vbus	2.128m	2.284ms	1	1	100.00
V2	chip_sw_usbdev_pullup	chip_sw_usbdev_pullup	2.480m	2.863ms	1	1	100.00
V2	chip_sw_usbdev_aon_pullup	chip_sw_usbdev_aon_pullup	4.271m	3.075ms	1	1	100.00
V2	chip_sw_usbdev_setup_rx	chip_sw_usbdev_setuprx	4.793m	3.957ms	1	1	100.00
V2	chip_sw_usbdev_config_host	chip_sw_usbdev_config_host	16.851m	8.422ms	1	1	100.00
V2	chip_sw_usbdev_pincfg	chip_sw_usbdev_pincfg	1.261h	31.499ms	1	1	100.00
V2	chip_sw_usbdev_tx_rx	chip_sw_usbdev_dpi	27.014m	11.750ms	1	1	100.00
V2	chip_sw_usbdev_toggle_restore	chip_sw_usbdev_toggle_restore	1.884m	3.174ms	1	1	100.00
V2		TOTAL			228	275	82.91
V2S	chip_sw_aes_masking_off	chip_sw_aes_masking_off	1.931m	2.707ms	1	1	100.00
V2S	chip_sw_rv_core_ibex_lockstep_glitch	chip_sw_rv_core_ibex_lockstep_glitch	1.556m	2.086ms	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	chip_sw_coremark	chip_sw_coremark	2.358h	71.913ms	1	1	100.00
V3	chip_sw_power_max_load	chip_sw_power_virus	13.272m	6.115ms	1	1	100.00
V3	rom_e2e_debug	rom_e2e_jtag_debug_test_unlocked0	15.625m	10.658ms	1	1	100.00
		rom_e2e_jtag_debug_dev	17.566m	11.947ms	1	1	100.00
		rom_e2e_jtag_debug_rma	16.581m	11.498ms	1	1	100.00
V3	rom_e2e_jtag_inject	rom_e2e_jtag_inject_test_unlocked0	48.553s		0	1	0.00
		rom_e2e_jtag_inject_dev	53.585s		0	1	0.00
		rom_e2e_jtag_inject_rma	37.656s		0	1	0.00
V3	rom_e2e_self_hash	rom_e2e_self_hash	13.589s		0	1	0.00
V3	chip_sw_clkmgr_jitter_cycle_measurements	chip_sw_clkmgr_jitter_frequency	9.004m	5.829ms	1	1	100.00
V3	chip_sw_edn_boot_mode	chip_sw_edn_boot_mode	4.445m	2.847ms	1	1	100.00
V3	chip_sw_edn_auto_mode	chip_sw_edn_auto_mode	11.308m	5.366ms	1	1	100.00
V3	chip_sw_edn_sw_mode	chip_sw_edn_sw_mode	22.356m	9.866ms	1	1	100.00
V3	chip_sw_edn_kat	chip_sw_edn_kat	3.452m	2.176ms	1	1	100.00
V3	chip_sw_flash_memory_protection	chip_sw_flash_ctrl_mem_protection	8.527m	5.070ms	1	1	100.00
V3	chip_sw_otp_ctrl_vendor_test_csr_access	chip_sw_otp_ctrl_vendor_test_csr_access	1.263m	2.396ms	1	1	100.00
V3	chip_sw_otp_ctrl_escalation	chip_sw_otp_ctrl_escalation	5.868m	5.883ms	1	1	100.00
V3	chip_sw_sensor_ctrl_deep_sleep_wake_up	chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up	3.933m	5.287ms	1	1	100.00
V3	chip_sw_pwrmgr_usb_clk_disabled_when_active	chip_sw_pwrmgr_usb_clk_disabled_when_active	5.624m	5.202ms	1	1	100.00
V3	chip_sw_all_resets	chip_sw_pwrmgr_all_reset_reqs	10.927m	8.485ms	1	1	100.00
V3	chip_rv_dm_perform_debug	rom_e2e_jtag_debug_test_unlocked0	15.625m	10.658ms	1	1	100.00
		rom_e2e_jtag_debug_dev	17.566m	11.947ms	1	1	100.00
		rom_e2e_jtag_debug_rma	16.581m	11.498ms	1	1	100.00
V3	chip_sw_rv_dm_access_after_hw_reset	chip_sw_rv_dm_access_after_escalation_reset	5.225m	5.522ms	1	1	100.00
V3	chip_sw_plic_alerts	chip_sw_all_escalation_resets	5.722m	5.139ms	1	1	100.00
V3	tick_configuration	chip_sw_rv_timer_systick_test	1.391h	37.749ms	1	1	100.00
V3	counter_wrap	chip_sw_rv_timer_systick_test	1.391h	37.749ms	1	1	100.00
V3	chip_sw_spi_device_output_when_disabled_or_sleeping	chip_sw_spi_device_pinmux_sleep_retention	2.215m	3.124ms	1	1	100.00
V3	chip_sw_uart_watermarks	chip_sw_uart_tx_rx	5.499m	4.752ms	1	1	100.00
V3	chip_sw_usbdev_stream	chip_sw_usbdev_stream	49.061m	19.140ms	1	1	100.00
V3		TOTAL			19	23	82.61
	Unmapped tests	chip_sival_flash_info_access	2.273m	2.776ms	1	1	100.00
		chip_sw_rstmgr_rst_cnsty_escalation	5.768m	4.768ms	1	1	100.00
		chip_sw_otp_ctrl_ecc_error_vendor_test	2.264m	2.411ms	1	1	100.00
		chip_sw_otp_ctrl_descrambling	2.615m	3.118ms	1	1	100.00
		chip_sw_pwrmgr_lowpower_cancel	4.209m	4.392ms	1	1	100.00
		chip_sw_pwrmgr_sleep_wake_5_bug	9.543s		0	1	0.00
		chip_sw_flash_ctrl_write_clear	3.056m	3.871ms	1	1	100.00
		TOTAL			273	325	84.00

Failure Buckets

Job returned non-zero exit code has 42 failures:

Test chip_sw_pwrmgr_sleep_wake_5_bug has 1 failures.

0.chip_sw_pwrmgr_sleep_wake_5_bug.229432931970810016671775010888918182241936742970252278392874285121116623499
Log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_sleep_wake_5_bug/latest/run.log

  Computing main repo mapping:
  Loading:
  Loading: 0 packages loaded
  WARNING: Target pattern parsing failed.
  ERROR: Skipping '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/runs/opentitan/sw/device/tests/BUILD
  ERROR: no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/runs/opentitan/sw/device/tests/BUILD
  INFO: Elapsed time: 0.159s
  INFO: 0 processes.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0 has 1 failures.

0.rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0.37076996000090863197053800404566191491109682519740039496771084533764681195843
Log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0/latest/run.log

      File "/nightly/runs/opentitan/rules/bitstreams.bzl", line 70, column 13, in _bitstreams_repo_impl
          fail("Bitstream cache not initialized properly.")
  Error in fail: Bitstream cache not initialized properly.
  ERROR: no such package '@@+_repo_rules+bitstreams//': Bitstream cache not initialized properly.
  ERROR: /nightly/runs/opentitan/hw/bitstream/BUILD:59:10: //hw/bitstream:bitstream depends on @@+_repo_rules+bitstreams//:chip_earlgrey_cw310_bitstream in repository @@+_repo_rules+bitstreams which failed to fetch. no such package '@@+_repo_rules+bitstreams//': Bitstream cache not initialized properly.
  ERROR: Analysis of target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' failed; build aborted: Analysis failed
  INFO: Elapsed time: 7.997s, Critical Path: 0.02s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test rom_e2e_boot_policy_valid_a_good_b_good_dev has 1 failures.

0.rom_e2e_boot_policy_valid_a_good_b_good_dev.106086671330925804328295960918519630821726121594857665873235379152559682558294
Log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_good_dev/latest/run.log

  Error in fail: Bitstream cache not initialized properly.
  ERROR: no such package '@@+_repo_rules+bitstreams//': Bitstream cache not initialized properly.
  ERROR: /nightly/runs/opentitan/hw/bitstream/BUILD:71:10: //hw/bitstream:cw310_mmi depends on @@+_repo_rules+bitstreams//:chip_earlgrey_cw310_mmi in repository @@+_repo_rules+bitstreams which failed to fetch. no such package '@@+_repo_rules+bitstreams//': Bitstream cache not initialized properly.
  Analyzing: target //sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv (0 packages loaded, 26279 targets configured)

  ERROR: Analysis of target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' failed; build aborted: Analysis failed
  INFO: Elapsed time: 3.195s, Critical Path: 0.02s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test rom_e2e_boot_policy_valid_a_good_b_good_prod has 1 failures.

0.rom_e2e_boot_policy_valid_a_good_b_good_prod.91612180662101891187050828961154573787900828704445225803017759444934745444203
Log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_good_prod/latest/run.log

  Error in fail: Bitstream cache not initialized properly.
  ERROR: no such package '@@+_repo_rules+bitstreams//': Bitstream cache not initialized properly.
  ERROR: /nightly/runs/opentitan/hw/bitstream/BUILD:59:10: //hw/bitstream:bitstream depends on @@+_repo_rules+bitstreams//:chip_earlgrey_cw310_bitstream in repository @@+_repo_rules+bitstreams which failed to fetch. no such package '@@+_repo_rules+bitstreams//': Bitstream cache not initialized properly.
  Analyzing: target //sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv (0 packages loaded, 26279 targets configured)

  ERROR: Analysis of target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' failed; build aborted: Analysis failed
  INFO: Elapsed time: 2.813s, Critical Path: 0.02s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test rom_e2e_boot_policy_valid_a_good_b_good_prod_end has 1 failures.

0.rom_e2e_boot_policy_valid_a_good_b_good_prod_end.13011867623544508652058933292609547641432200301964005701095685835074939535787
Log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_good_prod_end/latest/run.log

  Error in fail: Bitstream cache not initialized properly.
  ERROR: no such package '@@+_repo_rules+bitstreams//': Bitstream cache not initialized properly.
  ERROR: /nightly/runs/opentitan/hw/bitstream/BUILD:59:10: //hw/bitstream:bitstream depends on @@+_repo_rules+bitstreams//:chip_earlgrey_cw310_bitstream in repository @@+_repo_rules+bitstreams which failed to fetch. no such package '@@+_repo_rules+bitstreams//': Bitstream cache not initialized properly.
  Analyzing: target //sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv (0 packages loaded, 26279 targets configured)

  ERROR: Analysis of target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' failed; build aborted: Analysis failed
  INFO: Elapsed time: 2.122s, Critical Path: 0.02s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

... and 37 more tests.

UVM_ERROR @ * us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:379)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty has 1 failures:
- Test chip_sw_spi_device_pass_through_collision has 1 failures.
  - 0.chip_sw_spi_device_pass_through_collision.92255145144691207890007124598704005168752390961003797048648203415842668699452
    Line 416, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_spi_device_pass_through_collision/latest/run.log
```
  UVM_ERROR @ 3816.075864 us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:379)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty
  UVM_INFO @ 3816.075864 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR @ * us: (cip_base_scoreboard.sv:545) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@84877) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_sw_rstmgr_cpu_info has 1 failures.

0.chip_sw_rstmgr_cpu_info.114768711809524133091738928925597540665061707375158065351057418880690503902901
Line 455, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_rstmgr_cpu_info/latest/run.log

  UVM_ERROR @ 4179.373394 us: (cip_base_scoreboard.sv:545) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@84877) { a_addr: 'h8  a_data: 'h0  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h0  a_opcode: 'h0  a_user: 'h259aa  d_param: 'h0  d_source: 'h0  d_data: 'h0  d_size: 'h2  d_opcode: 'h0  d_error: 'h1  d_sink: 'h0  d_user: 'h1f2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 4179.373394 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (chip_sw_base_vseq.sv:317) virtual_sequencer [chip_sw_adc_ctrl_sleep_debug_cable_wakeup_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = * ns has 1 failures:
- Test chip_sw_adc_ctrl_sleep_debug_cable_wakeup has 1 failures.
  - 0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.14887514406042629774558826552435354959811241828291179954344161306374126826003
    Line 445, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup/latest/run.log
```
  UVM_ERROR @ 34841.843720 us: (chip_sw_base_vseq.sv:317) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_adc_ctrl_sleep_debug_cable_wakeup_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 18000000 ns

  UVM_INFO @ 34841.843720 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_test_sim_dv(hw/top_earlgrey/sw/autogen/tests/alert_test.c:307)] CHECK-fail: Expect alert *! has 1 failures:
- Test chip_sw_alert_test has 1 failures.
  - 0.chip_sw_alert_test.89669978832139029704917398720126077930268662802557346308188515378307177242436
    Line 406, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_alert_test/latest/run.log
```
  UVM_ERROR @ 3523.350044 us: (sw_logger_if.sv:526) [alert_test_sim_dv(hw/top_earlgrey/sw/autogen/tests/alert_test.c:307)] CHECK-fail: Expect alert 42!
  UVM_INFO @ 3523.350044 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0) has 1 failures:
- Test chip_sw_alert_handler_lpg_sleep_mode_alerts has 1 failures.
  - 0.chip_sw_alert_handler_lpg_sleep_mode_alerts.104616509315419168913587425904841424484231725463265571097279130382605049273661
    Line 405, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log
```
  UVM_ERROR @ 2693.118320 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
  UVM_INFO @ 2693.118320 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (cip_base_vseq.sv:587) [chip_sw_entropy_src_fuse_vseq] Check failed * == local_alert_agent_cfg.vif.get_alert() (* [*] vs * [*]) Alert usbdev_fatal_fault fired unexpectedly! has 1 failures:
- Test chip_sw_csrng_fuse_en_sw_app_read_test has 1 failures.
  - 0.chip_sw_csrng_fuse_en_sw_app_read_test.61873440808901959881495922083227260320970302021722524564699602977420414647139
    Line 408, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_csrng_fuse_en_sw_app_read_test/latest/run.log
```
  UVM_ERROR @ 2869.781107 us: (cip_base_vseq.sv:587) [uvm_test_top.env.virtual_sequencer.chip_sw_entropy_src_fuse_vseq] Check failed 0 == local_alert_agent_cfg.vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert usbdev_fatal_fault fired unexpectedly!
  UVM_INFO @ 2869.781107 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR @ * us: (cip_base_scoreboard.sv:545) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@33769) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_tl_errors has 1 failures.

0.chip_tl_errors.77025907432753596354000940289134199409368052287010182241008196840805954927389
Line 219, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_tl_errors/latest/run.log

  UVM_ERROR @ 2626.167112 us: (cip_base_scoreboard.sv:545) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@33769) { a_addr: 'h1077c  a_data: 'hee72dc08  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h14  a_opcode: 'h4  a_user: 'h19568  d_param: 'h0  d_source: 'h14  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 2626.167112 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (chip_sw_power_idle_load_vseq.sv:91) virtual_sequencer [chip_sw_power_idle_load_vseq] PWMCH* : pkt* Clock period is wrong. rcv : * exp : * has 1 failures:
- Test chip_sw_power_idle_load has 1 failures.
  - 0.chip_sw_power_idle_load.64505718230067907212848757327475947480860325534629283932015491926859391527435
    Line 415, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_power_idle_load/latest/run.log
```
  UVM_ERROR @ 3033.627000 us: (chip_sw_power_idle_load_vseq.sv:91) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_power_idle_load_vseq] PWMCH5 : pkt3 Clock period is wrong.  rcv : 2  exp : 32
  UVM_INFO @ 3033.627000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (chip_sw_power_sleep_load_vseq.sv:114) virtual_sequencer [chip_sw_power_sleep_load_vseq] PWMCH* : pkt* Clock period is wrong. rcv : * exp : * has 1 failures:
- Test chip_sw_power_sleep_load has 1 failures.
  - 0.chip_sw_power_sleep_load.93825576199750060815912235036578489827937220508712898875334290710332713143253
    Line 423, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_power_sleep_load/latest/run.log
```
  UVM_ERROR @ 3089.737000 us: (chip_sw_power_sleep_load_vseq.sv:114) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_power_sleep_load_vseq] PWMCH5 : pkt3 Clock period is wrong.  rcv : 2  exp : 32
  UVM_INFO @ 3089.737000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [ast_clk_rst_inputs_sim_dv(sw/device/tests/sim_dv/ast_clk_rst_inputs.c:147)] CHECK-fail: Recov alert not correctly observed in alert handler has 1 failures:
- Test chip_sw_ast_clk_rst_inputs has 1 failures.
  - 0.chip_sw_ast_clk_rst_inputs.56665320190361522332032662065733669692780387847673934808587152650138180597686
    Line 437, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_ast_clk_rst_inputs/latest/run.log
```
  UVM_ERROR @ 20686.943124 us: (sw_logger_if.sv:526) [ast_clk_rst_inputs_sim_dv(sw/device/tests/sim_dv/ast_clk_rst_inputs.c:147)] CHECK-fail: Recov alert not correctly observed in alert handler
  UVM_INFO @ 20686.943124 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```