ADC_CTRL Simulation Results

Thursday May 08 2025 20:26:01 UTC

GitHub Revision: 98096d3

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	adc_ctrl_smoke	3.650s	5.930ms	1	1	100.00
V1	csr_hw_reset	adc_ctrl_csr_hw_reset	3.900s	1.375ms	1	1	100.00
V1	csr_rw	adc_ctrl_csr_rw	2.020s	344.716us	1	1	100.00
V1	csr_bit_bash	adc_ctrl_csr_bit_bash	43.680s	26.267ms	1	1	100.00
V1	csr_aliasing	adc_ctrl_csr_aliasing	2.790s	1.130ms	1	1	100.00
V1	csr_mem_rw_with_rand_reset	adc_ctrl_csr_mem_rw_with_rand_reset	2.090s	471.371us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	adc_ctrl_csr_rw	2.020s	344.716us	1	1	100.00
		adc_ctrl_csr_aliasing	2.790s	1.130ms	1	1	100.00
V1		TOTAL			6	6	100.00
V2	filters_polled	adc_ctrl_filters_polled	4.461m	322.063ms	1	1	100.00
V2	filters_polled_fixed	adc_ctrl_filters_polled_fixed	34.080s	162.777ms	1	1	100.00
V2	filters_interrupt	adc_ctrl_filters_interrupt	3.989m	487.983ms	1	1	100.00
V2	filters_interrupt_fixed	adc_ctrl_filters_interrupt_fixed	4.767m	328.187ms	1	1	100.00
V2	filters_wakeup	adc_ctrl_filters_wakeup	3.939m	543.477ms	1	1	100.00
V2	filters_wakeup_fixed	adc_ctrl_filters_wakeup_fixed	1.221m	592.262ms	1	1	100.00
V2	filters_both	adc_ctrl_filters_both	1.922m	330.237ms	1	1	100.00
V2	clock_gating	adc_ctrl_clock_gating	2.400m	167.879ms	1	1	100.00
V2	poweron_counter	adc_ctrl_poweron_counter	7.310s	3.432ms	1	1	100.00
V2	lowpower_counter	adc_ctrl_lowpower_counter	40.700s	22.833ms	1	1	100.00
V2	fsm_reset	adc_ctrl_fsm_reset	46.520s	102.138ms	1	1	100.00
V2	stress_all	adc_ctrl_stress_all	4.764m	169.213ms	1	1	100.00
V2	alert_test	adc_ctrl_alert_test	2.780s	426.355us	1	1	100.00
V2	intr_test	adc_ctrl_intr_test	2.030s	394.841us	1	1	100.00
V2	tl_d_oob_addr_access	adc_ctrl_tl_errors	2.470s	645.480us	1	1	100.00
V2	tl_d_illegal_access	adc_ctrl_tl_errors	2.470s	645.480us	1	1	100.00
V2	tl_d_outstanding_access	adc_ctrl_csr_hw_reset	3.900s	1.375ms	1	1	100.00
		adc_ctrl_csr_rw	2.020s	344.716us	1	1	100.00
		adc_ctrl_csr_aliasing	2.790s	1.130ms	1	1	100.00
		adc_ctrl_same_csr_outstanding	3.240s	2.439ms	1	1	100.00
V2	tl_d_partial_access	adc_ctrl_csr_hw_reset	3.900s	1.375ms	1	1	100.00
		adc_ctrl_csr_rw	2.020s	344.716us	1	1	100.00
		adc_ctrl_csr_aliasing	2.790s	1.130ms	1	1	100.00
		adc_ctrl_same_csr_outstanding	3.240s	2.439ms	1	1	100.00
V2		TOTAL			16	16	100.00
V2S	tl_intg_err	adc_ctrl_sec_cm	4.200s	7.287ms	1	1	100.00
		adc_ctrl_tl_intg_err	5.800s	8.245ms	1	1	100.00
V2S	sec_cm_bus_integrity	adc_ctrl_tl_intg_err	5.800s	8.245ms	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	stress_all_with_rand_reset	adc_ctrl_stress_all_with_rand_reset	26.230m	10.000s	0	1	0.00
V3		TOTAL			0	1	0.00
		TOTAL			24	25	96.00

Failure Buckets

• UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
  • Test adc_ctrl_stress_all_with_rand_reset has 1 failures.

    • 0.adc_ctrl_stress_all_with_rand_reset.26023518603054101043943598568615408129289627008455270478658331029558036430564
      Line 180, in log /nightly/runs/scratch/master/adc_ctrl-sim-vcs/0.adc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_FATAL @ 10000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 10000000000000 ps hit, indicating a probable testbench issue
        UVM_INFO @ 10000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---