EDN Simulation Results

Thursday May 08 2025 20:26:01 UTC

GitHub Revision: 98096d3

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke edn_smoke 1.810s 20.131us 1 1 100.00
V1 csr_hw_reset edn_csr_hw_reset 1.760s 25.161us 1 1 100.00
V1 csr_rw edn_csr_rw 1.690s 17.371us 1 1 100.00
V1 csr_bit_bash edn_csr_bit_bash 4.640s 1.544ms 1 1 100.00
V1 csr_aliasing edn_csr_aliasing 1.750s 72.356us 1 1 100.00
V1 csr_mem_rw_with_rand_reset edn_csr_mem_rw_with_rand_reset 2.350s 95.486us 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr edn_csr_rw 1.690s 17.371us 1 1 100.00
edn_csr_aliasing 1.750s 72.356us 1 1 100.00
V1 TOTAL 6 6 100.00
V2 firmware edn_genbits 1.880s 198.709us 1 1 100.00
V2 csrng_commands edn_genbits 1.880s 198.709us 1 1 100.00
V2 genbits edn_genbits 1.880s 198.709us 1 1 100.00
V2 interrupts edn_intr 1.710s 26.306us 1 1 100.00
V2 alerts edn_alert 2.010s 48.336us 1 1 100.00
V2 errs edn_err 1.830s 20.800us 1 1 100.00
V2 disable edn_disable 1.630s 21.331us 1 1 100.00
edn_disable_auto_req_mode 1.910s 31.025us 1 1 100.00
V2 stress_all edn_stress_all 1.870s 57.420us 1 1 100.00
V2 intr_test edn_intr_test 1.610s 42.523us 1 1 100.00
V2 alert_test edn_alert_test 1.690s 31.261us 1 1 100.00
V2 tl_d_oob_addr_access edn_tl_errors 3.690s 561.689us 1 1 100.00
V2 tl_d_illegal_access edn_tl_errors 3.690s 561.689us 1 1 100.00
V2 tl_d_outstanding_access edn_csr_hw_reset 1.760s 25.161us 1 1 100.00
edn_csr_rw 1.690s 17.371us 1 1 100.00
edn_csr_aliasing 1.750s 72.356us 1 1 100.00
edn_same_csr_outstanding 2.000s 62.163us 1 1 100.00
V2 tl_d_partial_access edn_csr_hw_reset 1.760s 25.161us 1 1 100.00
edn_csr_rw 1.690s 17.371us 1 1 100.00
edn_csr_aliasing 1.750s 72.356us 1 1 100.00
edn_same_csr_outstanding 2.000s 62.163us 1 1 100.00
V2 TOTAL 11 11 100.00
V2S tl_intg_err edn_sec_cm 6.610s 6.068ms 1 1 100.00
edn_tl_intg_err 2.670s 90.416us 1 1 100.00
V2S sec_cm_config_regwen edn_regwen 1.640s 39.739us 1 1 100.00
V2S sec_cm_config_mubi edn_alert 2.010s 48.336us 1 1 100.00
V2S sec_cm_main_sm_fsm_sparse edn_sec_cm 6.610s 6.068ms 1 1 100.00
V2S sec_cm_ack_sm_fsm_sparse edn_sec_cm 6.610s 6.068ms 1 1 100.00
V2S sec_cm_fifo_ctr_redun edn_sec_cm 6.610s 6.068ms 1 1 100.00
V2S sec_cm_ctr_redun edn_sec_cm 6.610s 6.068ms 1 1 100.00
V2S sec_cm_main_sm_ctr_local_esc edn_alert 2.010s 48.336us 1 1 100.00
edn_sec_cm 6.610s 6.068ms 1 1 100.00
V2S sec_cm_cs_rdata_bus_consistency edn_alert 2.010s 48.336us 1 1 100.00
V2S sec_cm_tile_link_bus_integrity edn_tl_intg_err 2.670s 90.416us 1 1 100.00
V2S TOTAL 3 3 100.00
V3 stress_all_with_rand_reset edn_stress_all_with_rand_reset 0 1 0.00
V3 TOTAL 0 1 0.00
TOTAL 20 21 95.24

Failure Buckets