HMAC Simulation Results

Thursday May 08 2025 20:26:01 UTC

GitHub Revision: 98096d3

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke hmac_smoke 6.930s 699.219us 1 1 100.00
V1 csr_hw_reset hmac_csr_hw_reset 1.850s 34.170us 1 1 100.00
V1 csr_rw hmac_csr_rw 1.930s 116.351us 1 1 100.00
V1 csr_bit_bash hmac_csr_bit_bash 5.490s 464.551us 1 1 100.00
V1 csr_aliasing hmac_csr_aliasing 4.800s 111.289us 1 1 100.00
V1 csr_mem_rw_with_rand_reset hmac_csr_mem_rw_with_rand_reset 5.585m 45.295ms 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr hmac_csr_rw 1.930s 116.351us 1 1 100.00
hmac_csr_aliasing 4.800s 111.289us 1 1 100.00
V1 TOTAL 6 6 100.00
V2 long_msg hmac_long_msg 1.075m 1.542ms 1 1 100.00
V2 back_pressure hmac_back_pressure 1.192m 6.874ms 1 1 100.00
V2 test_vectors hmac_test_sha256_vectors 9.000s 736.682us 1 1 100.00
hmac_test_sha384_vectors 22.250s 212.653us 1 1 100.00
hmac_test_sha512_vectors 21.810s 981.002us 1 1 100.00
hmac_test_hmac256_vectors 13.250s 402.101us 1 1 100.00
hmac_test_hmac384_vectors 9.590s 1.024ms 1 1 100.00
hmac_test_hmac512_vectors 9.900s 220.507us 1 1 100.00
V2 burst_wr hmac_burst_wr 13.940s 1.087ms 1 1 100.00
V2 datapath_stress hmac_datapath_stress 8.994m 4.637ms 1 1 100.00
V2 error hmac_error 49.170s 1.145ms 1 1 100.00
V2 wipe_secret hmac_wipe_secret 1.305m 11.964ms 1 1 100.00
V2 save_and_restore hmac_smoke 6.930s 699.219us 1 1 100.00
hmac_long_msg 1.075m 1.542ms 1 1 100.00
hmac_back_pressure 1.192m 6.874ms 1 1 100.00
hmac_datapath_stress 8.994m 4.637ms 1 1 100.00
hmac_burst_wr 13.940s 1.087ms 1 1 100.00
hmac_stress_all 18.303m 45.100ms 1 1 100.00
V2 fifo_empty_status_interrupt hmac_smoke 6.930s 699.219us 1 1 100.00
hmac_long_msg 1.075m 1.542ms 1 1 100.00
hmac_back_pressure 1.192m 6.874ms 1 1 100.00
hmac_datapath_stress 8.994m 4.637ms 1 1 100.00
hmac_wipe_secret 1.305m 11.964ms 1 1 100.00
hmac_test_sha256_vectors 9.000s 736.682us 1 1 100.00
hmac_test_sha384_vectors 22.250s 212.653us 1 1 100.00
hmac_test_sha512_vectors 21.810s 981.002us 1 1 100.00
hmac_test_hmac256_vectors 13.250s 402.101us 1 1 100.00
hmac_test_hmac384_vectors 9.590s 1.024ms 1 1 100.00
hmac_test_hmac512_vectors 9.900s 220.507us 1 1 100.00
V2 wide_digest_configurable_key_length hmac_smoke 6.930s 699.219us 1 1 100.00
hmac_long_msg 1.075m 1.542ms 1 1 100.00
hmac_back_pressure 1.192m 6.874ms 1 1 100.00
hmac_datapath_stress 8.994m 4.637ms 1 1 100.00
hmac_burst_wr 13.940s 1.087ms 1 1 100.00
hmac_error 49.170s 1.145ms 1 1 100.00
hmac_wipe_secret 1.305m 11.964ms 1 1 100.00
hmac_test_sha256_vectors 9.000s 736.682us 1 1 100.00
hmac_test_sha384_vectors 22.250s 212.653us 1 1 100.00
hmac_test_sha512_vectors 21.810s 981.002us 1 1 100.00
hmac_test_hmac256_vectors 13.250s 402.101us 1 1 100.00
hmac_test_hmac384_vectors 9.590s 1.024ms 1 1 100.00
hmac_test_hmac512_vectors 9.900s 220.507us 1 1 100.00
hmac_stress_all 18.303m 45.100ms 1 1 100.00
V2 stress_all hmac_stress_all 18.303m 45.100ms 1 1 100.00
V2 alert_test hmac_alert_test 1.580s 35.227us 1 1 100.00
V2 intr_test hmac_intr_test 1.570s 122.464us 1 1 100.00
V2 tl_d_oob_addr_access hmac_tl_errors 3.580s 177.670us 1 1 100.00
V2 tl_d_illegal_access hmac_tl_errors 3.580s 177.670us 1 1 100.00
V2 tl_d_outstanding_access hmac_csr_hw_reset 1.850s 34.170us 1 1 100.00
hmac_csr_rw 1.930s 116.351us 1 1 100.00
hmac_csr_aliasing 4.800s 111.289us 1 1 100.00
hmac_same_csr_outstanding 2.950s 544.584us 1 1 100.00
V2 tl_d_partial_access hmac_csr_hw_reset 1.850s 34.170us 1 1 100.00
hmac_csr_rw 1.930s 116.351us 1 1 100.00
hmac_csr_aliasing 4.800s 111.289us 1 1 100.00
hmac_same_csr_outstanding 2.950s 544.584us 1 1 100.00
V2 TOTAL 17 17 100.00
V2S tl_intg_err hmac_sec_cm 2.010s 69.118us 1 1 100.00
hmac_tl_intg_err 3.510s 2.193ms 1 1 100.00
V2S sec_cm_bus_integrity hmac_tl_intg_err 3.510s 2.193ms 1 1 100.00
V2S TOTAL 2 2 100.00
V3 write_config_and_secret_key_during_msg_wr hmac_smoke 6.930s 699.219us 1 1 100.00
V3 stress_reset hmac_stress_reset 3.580s 271.972us 1 1 100.00
V3 stress_all_with_rand_reset hmac_stress_all_with_rand_reset 27.020s 9.620ms 1 1 100.00
V3 TOTAL 2 2 100.00
Unmapped tests hmac_directed 1.910s 25.406us 1 1 100.00
TOTAL 28 28 100.00