I2C Simulation Results

Thursday May 08 2025 20:26:01 UTC

GitHub Revision: `98096d3`

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	host_smoke	i2c_host_smoke	43.140s	5.226ms	1	1	100.00
V1	target_smoke	i2c_target_smoke	12.590s	6.978ms	1	1	100.00
V1	csr_hw_reset	i2c_csr_hw_reset	1.590s	32.470us	1	1	100.00
V1	csr_rw	i2c_csr_rw	1.570s	113.004us	1	1	100.00
V1	csr_bit_bash	i2c_csr_bit_bash	3.070s	470.628us	1	1	100.00
V1	csr_aliasing	i2c_csr_aliasing	1.920s	54.124us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	i2c_csr_mem_rw_with_rand_reset	2.240s	21.964us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	i2c_csr_rw	1.570s	113.004us	1	1	100.00
		i2c_csr_aliasing	1.920s	54.124us	1	1	100.00
V1		TOTAL			7	7	100.00
V2	host_error_intr	i2c_host_error_intr	3.310s	396.613us	1	1	100.00
V2	host_stress_all	i2c_host_stress_all	3.572m	10.005ms	0	1	0.00
V2	host_maxperf	i2c_host_perf	27.150s	5.665ms	1	1	100.00
V2	host_override	i2c_host_override	1.840s	20.791us	1	1	100.00
V2	host_fifo_watermark	i2c_host_fifo_watermark	1.668m	21.624ms	1	1	100.00
V2	host_fifo_overflow	i2c_host_fifo_overflow	1.195m	13.521ms	1	1	100.00
V2	host_fifo_reset	i2c_host_fifo_reset_fmt	1.980s	336.388us	1	1	100.00
		i2c_host_fifo_fmt_empty	13.450s	795.022us	1	1	100.00
		i2c_host_fifo_reset_rx	6.100s	177.213us	1	1	100.00
V2	host_fifo_full	i2c_host_fifo_full	34.580s	1.885ms	1	1	100.00
V2	host_timeout	i2c_host_stretch_timeout	30.910s	5.457ms	1	1	100.00
V2	i2c_host_mode_toggle	i2c_host_mode_toggle	1.630s	27.664us	0	1	0.00
V2	target_glitch	i2c_target_glitch	8.610s	8.181ms	1	1	100.00
V2	target_stress_all	i2c_target_stress_all	1.089m	52.526ms	1	1	100.00
V2	target_maxperf	i2c_target_perf	4.130s	540.595us	1	1	100.00
V2	target_fifo_empty	i2c_target_stress_rd	15.220s	1.282ms	1	1	100.00
		i2c_target_intr_smoke	5.230s	2.109ms	1	1	100.00
V2	target_fifo_reset	i2c_target_fifo_reset_acq	2.270s	536.913us	1	1	100.00
		i2c_target_fifo_reset_tx	2.310s	786.842us	1	1	100.00
V2	target_fifo_full	i2c_target_stress_wr	21.940s	24.824ms	1	1	100.00
		i2c_target_stress_rd	15.220s	1.282ms	1	1	100.00
		i2c_target_intr_stress_wr	45.870s	12.561ms	1	1	100.00
V2	target_timeout	i2c_target_timeout	5.780s	5.611ms	1	1	100.00
V2	target_clock_stretch	i2c_target_stretch	2.270s	287.641us	1	1	100.00
V2	bad_address	i2c_target_bad_addr	5.330s	1.207ms	1	1	100.00
V2	target_mode_glitch	i2c_target_hrst	3.010s	999.973us	1	1	100.00
V2	target_fifo_watermark	i2c_target_fifo_watermarks_acq	2.630s	390.997us	1	1	100.00
		i2c_target_fifo_watermarks_tx	2.010s	57.907us	1	1	100.00
V2	host_mode_config_perf	i2c_host_perf	27.150s	5.665ms	1	1	100.00
		i2c_host_perf_precise	17.470s	3.093ms	1	1	100.00
V2	host_mode_clock_stretching	i2c_host_stretch_timeout	30.910s	5.457ms	1	1	100.00
V2	target_mode_tx_stretch_ctrl	i2c_target_tx_stretch_ctrl	2.610s	48.696us	1	1	100.00
V2	target_mode_nack_generation	i2c_target_nack_acqfull	3.430s	3.605ms	1	1	100.00
		i2c_target_nack_acqfull_addr	3.020s	2.174ms	1	1	100.00
		i2c_target_nack_txstretch	2.600s	629.472us	1	1	100.00
V2	host_mode_halt_on_nak	i2c_host_may_nack	12.050s	396.799us	1	1	100.00
V2	target_mode_smbus_maxlen	i2c_target_smbus_maxlen	3.370s	1.933ms	1	1	100.00
V2	alert_test	i2c_alert_test	1.450s	28.095us	1	1	100.00
V2	intr_test	i2c_intr_test	1.980s	16.781us	1	1	100.00
V2	tl_d_oob_addr_access	i2c_tl_errors	2.470s	43.494us	1	1	100.00
V2	tl_d_illegal_access	i2c_tl_errors	2.470s	43.494us	1	1	100.00
V2	tl_d_outstanding_access	i2c_csr_hw_reset	1.590s	32.470us	1	1	100.00
		i2c_csr_rw	1.570s	113.004us	1	1	100.00
		i2c_csr_aliasing	1.920s	54.124us	1	1	100.00
		i2c_same_csr_outstanding	1.610s	22.436us	1	1	100.00
V2	tl_d_partial_access	i2c_csr_hw_reset	1.590s	32.470us	1	1	100.00
		i2c_csr_rw	1.570s	113.004us	1	1	100.00
		i2c_csr_aliasing	1.920s	54.124us	1	1	100.00
		i2c_same_csr_outstanding	1.610s	22.436us	1	1	100.00
V2		TOTAL			36	38	94.74
V2S	tl_intg_err	i2c_tl_intg_err	3.370s	1.921ms	1	1	100.00
		i2c_sec_cm	1.940s	75.600us	1	1	100.00
V2S	sec_cm_bus_integrity	i2c_tl_intg_err	3.370s	1.921ms	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	host_stress_all_with_rand_reset	i2c_host_stress_all_with_rand_reset	8.770s	600.778us	0	1	0.00
V3	target_error_intr	i2c_target_unexp_stop	1.970s	194.723us	0	1	0.00
V3	target_stress_all_with_rand_reset	i2c_target_stress_all_with_rand_reset	13.030s	4.060ms	0	1	0.00
V3		TOTAL			0	3	0.00
		TOTAL			45	50	90.00

Failure Buckets

UVM_ERROR (i2c_scoreboard.sv:716) [scoreboard] controller_mode_rd_obs_fifo item uncompared: has 1 failures:

Test i2c_host_stress_all has 1 failures.

0.i2c_host_stress_all.66418394054406505756674313259068815528669635496313424434337804309261508004420
Line 193, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_host_stress_all/latest/run.log

  UVM_ERROR @ 10004568169 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
  ----------------------------------------------------
  Name            Type                Size  Value
  ----------------------------------------------------
  mon_dut_item    i2c_item            -     @2884638

UVM_ERROR (i2c_scoreboard.sv:682) [scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (* [*] vs * [*]) has 1 failures:
- Test i2c_target_unexp_stop has 1 failures.
  - 0.i2c_target_unexp_stop.7883117951539183042105667312225938797305812452942696088857153145735062310912
    Line 73, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_target_unexp_stop/latest/run.log
```
  UVM_ERROR @ 194722814 ps: (i2c_scoreboard.sv:682) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 26 [0x1a])
  UVM_INFO @ 194722814 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_vseq.sv:928) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:
- Test i2c_host_stress_all_with_rand_reset has 1 failures.
  - 0.i2c_host_stress_all_with_rand_reset.59563732217519980996573378479057128597408776344137402127373013546423392539925
    Line 89, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_host_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 600778232 ps: (cip_base_vseq.sv:928) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 600778232 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (i2c_base_vseq.sv:760) [i2c_target_timeout_vseq] Check failed (cfg.m_i2c_agent_cfg.rcvd_rd_byte == *) has 1 failures:
- Test i2c_target_stress_all_with_rand_reset has 1 failures.
  - 0.i2c_target_stress_all_with_rand_reset.58384935732937746902216930619086406369874244884057434577298431542768268619467
    Line 131, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_target_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 4059736289 ps: (i2c_base_vseq.sv:760) [uvm_test_top.env.virtual_sequencer.i2c_target_timeout_vseq] Check failed (cfg.m_i2c_agent_cfg.rcvd_rd_byte == 0)
  UVM_INFO @ 4059736289 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout i2c_reg_block.status.hostidle (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=3) has 1 failures:
- Test i2c_host_mode_toggle has 1 failures.
  - 0.i2c_host_mode_toggle.100878131854989445583136310482234351428121262810111761148279099230813422391055
    Line 74, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_host_mode_toggle/latest/run.log
```
  UVM_FATAL @  27663726 ps: (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout i2c_reg_block.status.hostidle (addr=0x7d409e94, Comparison=CompareOpEq, exp_data=0x1, call_count=3)
  UVM_INFO @  27663726 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```