KMAC/MASKED Simulation Results

Thursday May 08 2025 20:26:01 UTC

GitHub Revision: 98096d3

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	55.330s	3.551ms	1	1	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	1.670s	31.702us	1	1	100.00
V1	csr_rw	kmac_csr_rw	1.550s	38.940us	1	1	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	12.550s	1.995ms	1	1	100.00
V1	csr_aliasing	kmac_csr_aliasing	4.200s	395.952us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	2.220s	41.995us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	1.550s	38.940us	1	1	100.00
		kmac_csr_aliasing	4.200s	395.952us	1	1	100.00
V1	mem_walk	kmac_mem_walk	1.490s	33.330us	1	1	100.00
V1	mem_partial_access	kmac_mem_partial_access	1.920s	65.459us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	14.024m	87.548ms	1	1	100.00
V2	burst_write	kmac_burst_write	6.439m	11.034ms	1	1	100.00
V2	test_vectors	kmac_test_vectors_sha3_224	27.250s	1.246ms	1	1	100.00
		kmac_test_vectors_sha3_256	28.947m	232.572ms	1	1	100.00
		kmac_test_vectors_sha3_384	1.800s	60.124us	0	1	0.00
		kmac_test_vectors_sha3_512	12.220s	551.397us	1	1	100.00
		kmac_test_vectors_shake_128	26.792m	42.540ms	1	1	100.00
		kmac_test_vectors_shake_256	4.781m	21.441ms	1	1	100.00
		kmac_test_vectors_kmac	2.680s	237.948us	1	1	100.00
		kmac_test_vectors_kmac_xof	2.920s	284.871us	1	1	100.00
V2	sideload	kmac_sideload	6.260s	210.134us	1	1	100.00
V2	app	kmac_app	30.170s	1.978ms	1	1	100.00
V2	app_with_partial_data	kmac_app_with_partial_data	5.760s	202.149us	1	1	100.00
V2	entropy_refresh	kmac_entropy_refresh	4.849m	20.976ms	1	1	100.00
V2	error	kmac_error	1.601m	1.941ms	1	1	100.00
V2	key_error	kmac_key_error	4.230s	483.407us	1	1	100.00
V2	sideload_invalid	kmac_sideload_invalid	7.440s	1.112ms	1	1	100.00
V2	edn_timeout_error	kmac_edn_timeout_error	1.520s	25.066us	1	1	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	1.530s	39.045us	1	1	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	5.100s	1.149ms	1	1	100.00
V2	lc_escalation	kmac_lc_escalation	1.940s	34.857us	1	1	100.00
V2	stress_all	kmac_stress_all	25.568m	93.446ms	1	1	100.00
V2	intr_test	kmac_intr_test	1.580s	11.639us	1	1	100.00
V2	alert_test	kmac_alert_test	1.510s	79.912us	1	1	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	3.020s	417.094us	1	1	100.00
V2	tl_d_illegal_access	kmac_tl_errors	3.020s	417.094us	1	1	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	1.670s	31.702us	1	1	100.00
		kmac_csr_rw	1.550s	38.940us	1	1	100.00
		kmac_csr_aliasing	4.200s	395.952us	1	1	100.00
		kmac_same_csr_outstanding	2.080s	57.964us	1	1	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	1.670s	31.702us	1	1	100.00
		kmac_csr_rw	1.550s	38.940us	1	1	100.00
		kmac_csr_aliasing	4.200s	395.952us	1	1	100.00
		kmac_same_csr_outstanding	2.080s	57.964us	1	1	100.00
V2		TOTAL			25	26	96.15
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	2.050s	97.985us	1	1	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	2.050s	97.985us	1	1	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	2.050s	97.985us	1	1	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	2.050s	97.985us	1	1	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	2.600s	52.234us	1	1	100.00
V2S	tl_intg_err	kmac_sec_cm	24.200s	2.949ms	1	1	100.00
		kmac_tl_intg_err	2.780s	964.767us	1	1	100.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	2.780s	964.767us	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	1.940s	34.857us	1	1	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	55.330s	3.551ms	1	1	100.00
V2S	sec_cm_key_sideload	kmac_sideload	6.260s	210.134us	1	1	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	2.050s	97.985us	1	1	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	24.200s	2.949ms	1	1	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	24.200s	2.949ms	1	1	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	24.200s	2.949ms	1	1	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	55.330s	3.551ms	1	1	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	1.940s	34.857us	1	1	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	24.200s	2.949ms	1	1	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	3.251m	22.768ms	1	1	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	55.330s	3.551ms	1	1	100.00
V2S		TOTAL			5	5	100.00
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	1.702m	18.931ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			39	40	97.50

Failure Buckets

• UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: kmac_reg_block.intr_state.kmac_done reset value: * has 1 failures:
  • Test kmac_test_vectors_sha3_384 has 1 failures.

    • 0.kmac_test_vectors_sha3_384.52123681338304734076607118546594954090783277446333096704420206924220965141348
      Line 73, in log /nightly/runs/scratch/master/kmac_masked-sim-vcs/0.kmac_test_vectors_sha3_384/latest/run.log

        UVM_ERROR @  60124350 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
        UVM_INFO @  60124350 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---