KMAC/UNMASKED Simulation Results

Thursday May 08 2025 20:26:01 UTC

GitHub Revision: 98096d3

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	21.160s	592.637us	1	1	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	1.780s	35.653us	1	1	100.00
V1	csr_rw	kmac_csr_rw	1.840s	14.564us	1	1	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	19.860s	6.007ms	1	1	100.00
V1	csr_aliasing	kmac_csr_aliasing	4.720s	1.096ms	1	1	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	3.160s	67.816us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	1.840s	14.564us	1	1	100.00
		kmac_csr_aliasing	4.720s	1.096ms	1	1	100.00
V1	mem_walk	kmac_mem_walk	1.560s	23.534us	1	1	100.00
V1	mem_partial_access	kmac_mem_partial_access	2.220s	31.459us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	20.538m	74.670ms	1	1	100.00
V2	burst_write	kmac_burst_write	40.350s	1.200ms	1	1	100.00
V2	test_vectors	kmac_test_vectors_sha3_224	24.360s	2.551ms	1	1	100.00
		kmac_test_vectors_sha3_256	29.660s	2.074ms	1	1	100.00
		kmac_test_vectors_sha3_384	18.690s	6.642ms	1	1	100.00
		kmac_test_vectors_sha3_512	12.535m	383.883ms	1	1	100.00
		kmac_test_vectors_shake_128	2.358m	190.759ms	1	1	100.00
		kmac_test_vectors_shake_256	3.413m	11.250ms	1	1	100.00
		kmac_test_vectors_kmac	3.210s	148.243us	1	1	100.00
		kmac_test_vectors_kmac_xof	2.530s	30.575us	1	1	100.00
V2	sideload	kmac_sideload	4.427m	17.569ms	1	1	100.00
V2	app	kmac_app	43.840s	10.184ms	1	1	100.00
V2	app_with_partial_data	kmac_app_with_partial_data	1.871m	19.401ms	1	1	100.00
V2	entropy_refresh	kmac_entropy_refresh	1.278m	7.829ms	1	1	100.00
V2	error	kmac_error	54.710s	2.068ms	1	1	100.00
V2	key_error	kmac_key_error	5.320s	1.248ms	1	1	100.00
V2	sideload_invalid	kmac_sideload_invalid	4.310s	170.048us	1	1	100.00
V2	edn_timeout_error	kmac_edn_timeout_error	26.900s	7.178ms	1	1	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	23.430s	10.110ms	1	1	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	18.340s	2.886ms	1	1	100.00
V2	lc_escalation	kmac_lc_escalation	2.120s	40.199us	1	1	100.00
V2	stress_all	kmac_stress_all	8.444m	182.889ms	1	1	100.00
V2	intr_test	kmac_intr_test	2.110s	18.997us	1	1	100.00
V2	alert_test	kmac_alert_test	1.640s	47.448us	1	1	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	2.890s	318.475us	1	1	100.00
V2	tl_d_illegal_access	kmac_tl_errors	2.890s	318.475us	1	1	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	1.780s	35.653us	1	1	100.00
		kmac_csr_rw	1.840s	14.564us	1	1	100.00
		kmac_csr_aliasing	4.720s	1.096ms	1	1	100.00
		kmac_same_csr_outstanding	3.250s	96.552us	1	1	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	1.780s	35.653us	1	1	100.00
		kmac_csr_rw	1.840s	14.564us	1	1	100.00
		kmac_csr_aliasing	4.720s	1.096ms	1	1	100.00
		kmac_same_csr_outstanding	3.250s	96.552us	1	1	100.00
V2		TOTAL			26	26	100.00
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	1.950s	85.307us	1	1	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	1.950s	85.307us	1	1	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	1.950s	85.307us	1	1	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	1.950s	85.307us	1	1	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	1.730s	19.732us	0	1	0.00
V2S	tl_intg_err	kmac_sec_cm	27.840s	2.835ms	1	1	100.00
		kmac_tl_intg_err	1.860s	45.676us	0	1	0.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	1.860s	45.676us	0	1	0.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	2.120s	40.199us	1	1	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	21.160s	592.637us	1	1	100.00
V2S	sec_cm_key_sideload	kmac_sideload	4.427m	17.569ms	1	1	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	1.950s	85.307us	1	1	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	27.840s	2.835ms	1	1	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	27.840s	2.835ms	1	1	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	27.840s	2.835ms	1	1	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	21.160s	592.637us	1	1	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	2.120s	40.199us	1	1	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	27.840s	2.835ms	1	1	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	13.900s	364.049us	1	1	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	21.160s	592.637us	1	1	100.00
V2S		TOTAL			3	5	60.00
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	1.326m	1.309ms	0	1	0.00
V3		TOTAL			0	1	0.00
		TOTAL			37	40	92.50

Failure Buckets

• Offending '(d2h.d_error || ((d2h.d_data & *) == (exp_vals[*] & *)))' has 2 failures:

  • Test kmac_shadow_reg_errors_with_csr_rw has 1 failures.

    • 0.kmac_shadow_reg_errors_with_csr_rw.105224855637695686944218317110086844205605058907337636546244322542235885526362
      Line 86, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/0.kmac_shadow_reg_errors_with_csr_rw/latest/run.log

            Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[41] & 'hffffffff)))'
        UVM_ERROR @  19731806 ps: (kmac_csr_assert_fpv.sv:502) [ASSERT FAILED] prefix_2_rd_A
        UVM_INFO @  19731806 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test kmac_tl_intg_err has 1 failures.

    • 0.kmac_tl_intg_err.103690107149023972273573921225125712666975747566466928948097115408672756513938
      Line 75, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/0.kmac_tl_intg_err/latest/run.log

            Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[42] & 'hffffffff)))'
        UVM_ERROR @  45675594 ps: (kmac_csr_assert_fpv.sv:507) [ASSERT FAILED] prefix_3_rd_A
        UVM_INFO @  45675594 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (kmac_scoreboard.sv:1202) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: kmac_reg_block.err_code has 1 failures:

  • Test kmac_stress_all_with_rand_reset has 1 failures.

    • 0.kmac_stress_all_with_rand_reset.16993189223220911669581775576272613569681160248244809976274051946687853805763
      Line 135, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/0.kmac_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 1308921523 ps: (kmac_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483712 [0x80000040]) reg name: kmac_reg_block.err_code
        UVM_INFO @ 1308921523 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---