PATTGEN Simulation Results

Thursday May 08 2025 20:26:01 UTC

GitHub Revision: `98096d3`

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	pattgen_smoke	4.000s	27.086us	1	1	100.00
V1	csr_hw_reset	pattgen_csr_hw_reset	13.000s	63.503us	1	1	100.00
V1	csr_rw	pattgen_csr_rw	13.000s	14.946us	1	1	100.00
V1	csr_bit_bash	pattgen_csr_bit_bash	11.000s	256.260us	1	1	100.00
V1	csr_aliasing	pattgen_csr_aliasing	11.000s	87.308us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	pattgen_csr_mem_rw_with_rand_reset	10.000s	150.638us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	pattgen_csr_rw	13.000s	14.946us	1	1	100.00
		pattgen_csr_aliasing	11.000s	87.308us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	perf	pattgen_perf	21.100m	600.000ms	0	1	0.00
V2	cnt_rollover	cnt_rollover	36.000s	5.742ms	1	1	100.00
V2	error	pattgen_error	4.000s	579.650us	1	1	100.00
V2	stress_all	pattgen_stress_all	16.000s	1.497ms	0	1	0.00
V2	alert_test	pattgen_alert_test	4.000s	62.177us	1	1	100.00
V2	intr_test	pattgen_intr_test	15.000s	13.899us	1	1	100.00
V2	tl_d_oob_addr_access	pattgen_tl_errors	15.000s	89.275us	1	1	100.00
V2	tl_d_illegal_access	pattgen_tl_errors	15.000s	89.275us	1	1	100.00
V2	tl_d_outstanding_access	pattgen_csr_hw_reset	13.000s	63.503us	1	1	100.00
		pattgen_csr_rw	13.000s	14.946us	1	1	100.00
		pattgen_csr_aliasing	11.000s	87.308us	1	1	100.00
		pattgen_same_csr_outstanding	10.000s	24.167us	1	1	100.00
V2	tl_d_partial_access	pattgen_csr_hw_reset	13.000s	63.503us	1	1	100.00
		pattgen_csr_rw	13.000s	14.946us	1	1	100.00
		pattgen_csr_aliasing	11.000s	87.308us	1	1	100.00
		pattgen_same_csr_outstanding	10.000s	24.167us	1	1	100.00
V2		TOTAL			6	8	75.00
V2S	tl_intg_err	pattgen_tl_intg_err	15.000s	304.153us	1	1	100.00
		pattgen_sec_cm	3.000s	821.588us	1	1	100.00
V2S	sec_cm_bus_integrity	pattgen_tl_intg_err	15.000s	304.153us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	stress_all_with_rand_reset	pattgen_stress_all_with_rand_reset	21.000s	2.476ms	0	1	0.00
V3		TOTAL			0	1	0.00
	Unmapped tests	pattgen_inactive_level	4.000s	100.547us	1	1	100.00
		TOTAL			15	18	83.33

Failure Buckets

UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
- Test pattgen_perf has 1 failures.
  - 0.pattgen_perf.17348801787463800240190411154673756881504990743132073019465219494537369467985
    Line 96, in log /nightly/runs/scratch/master/pattgen-sim-xcelium/0.pattgen_perf/latest/run.log
```
  UVM_FATAL @ 600000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 600000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR (cip_base_vseq.sv:929) [pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:

Test pattgen_stress_all_with_rand_reset has 1 failures.

0.pattgen_stress_all_with_rand_reset.8384785348165532623060274733020338867615429059741990487297876895943875497113
Line 194, in log /nightly/runs/scratch/master/pattgen-sim-xcelium/0.pattgen_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 1851737903 ps: (cip_base_vseq.sv:929) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_ERROR @ 1851743599 ps: (cip_base_vseq.sv:833) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 1851743599 ps: (cip_base_vseq.sv:836) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
  Issuing reset for run 3/5
  UVM_INFO @ 1851774850 ps: (cip_base_vseq.sv:857) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]

UVM_ERROR (pattgen_scoreboard.sv:76) [scoreboard] exp_item_q[i] item uncompared: has 1 failures:
- Test pattgen_stress_all has 1 failures.
  - 0.pattgen_stress_all.114174852061021649541109587298142216828800657284409805210192755713219862271247
    Line 145, in log /nightly/runs/scratch/master/pattgen-sim-xcelium/0.pattgen_stress_all/latest/run.log
```
  UVM_ERROR @ 1496658492 ps: (pattgen_scoreboard.sv:76) [uvm_test_top.env.scoreboard] exp_item_q[i] item uncompared:
  ------------------------------------
  Name      Type          Size  Value
  ------------------------------------
  exp_item  pattgen_item  -     @10359
```