ROM_CTRL/32KB Simulation Results

Thursday May 08 2025 20:26:01 UTC

GitHub Revision: 98096d3

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	rom_ctrl_smoke	6.820s	1.066ms	1	1	100.00
V1	csr_hw_reset	rom_ctrl_csr_hw_reset	6.480s	364.815us	1	1	100.00
V1	csr_rw	rom_ctrl_csr_rw	4.560s	555.024us	1	1	100.00
V1	csr_bit_bash	rom_ctrl_csr_bit_bash	5.420s	173.283us	1	1	100.00
V1	csr_aliasing	rom_ctrl_csr_aliasing	4.630s	554.985us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	rom_ctrl_csr_mem_rw_with_rand_reset	4.710s	962.760us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rom_ctrl_csr_rw	4.560s	555.024us	1	1	100.00
		rom_ctrl_csr_aliasing	4.630s	554.985us	1	1	100.00
V1	mem_walk	rom_ctrl_mem_walk	6.160s	303.587us	1	1	100.00
V1	mem_partial_access	rom_ctrl_mem_partial_access	4.430s	1.804ms	1	1	100.00
V1		TOTAL			8	8	100.00
V2	max_throughput_chk	rom_ctrl_max_throughput_chk	6.350s	807.216us	1	1	100.00
V2	stress_all	rom_ctrl_stress_all	17.250s	6.618ms	1	1	100.00
V2	kmac_err_chk	rom_ctrl_kmac_err_chk	8.510s	1.561ms	1	1	100.00
V2	alert_test	rom_ctrl_alert_test	3.960s	209.911us	1	1	100.00
V2	tl_d_oob_addr_access	rom_ctrl_tl_errors	5.910s	135.869us	1	1	100.00
V2	tl_d_illegal_access	rom_ctrl_tl_errors	5.910s	135.869us	1	1	100.00
V2	tl_d_outstanding_access	rom_ctrl_csr_hw_reset	6.480s	364.815us	1	1	100.00
		rom_ctrl_csr_rw	4.560s	555.024us	1	1	100.00
		rom_ctrl_csr_aliasing	4.630s	554.985us	1	1	100.00
		rom_ctrl_same_csr_outstanding	5.350s	126.429us	1	1	100.00
V2	tl_d_partial_access	rom_ctrl_csr_hw_reset	6.480s	364.815us	1	1	100.00
		rom_ctrl_csr_rw	4.560s	555.024us	1	1	100.00
		rom_ctrl_csr_aliasing	4.630s	554.985us	1	1	100.00
		rom_ctrl_same_csr_outstanding	5.350s	126.429us	1	1	100.00
V2		TOTAL			6	6	100.00
V2S	corrupt_sig_fatal_chk	rom_ctrl_corrupt_sig_fatal_chk	33.440s	568.217us	0	1	0.00
V2S	passthru_mem_tl_intg_err	rom_ctrl_passthru_mem_tl_intg_err	20.130s	2.559ms	1	1	100.00
V2S	tl_intg_err	rom_ctrl_sec_cm	2.961m	2.283ms	1	1	100.00
		rom_ctrl_tl_intg_err	42.170s	1.112ms	1	1	100.00
V2S	prim_fsm_check	rom_ctrl_sec_cm	2.961m	2.283ms	1	1	100.00
V2S	prim_count_check	rom_ctrl_sec_cm	2.961m	2.283ms	1	1	100.00
V2S	sec_cm_checker_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	33.440s	568.217us	0	1	0.00
V2S	sec_cm_checker_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	33.440s	568.217us	0	1	0.00
V2S	sec_cm_checker_fsm_local_esc	rom_ctrl_corrupt_sig_fatal_chk	33.440s	568.217us	0	1	0.00
V2S	sec_cm_compare_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	33.440s	568.217us	0	1	0.00
V2S	sec_cm_compare_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	33.440s	568.217us	0	1	0.00
V2S	sec_cm_compare_ctr_redun	rom_ctrl_sec_cm	2.961m	2.283ms	1	1	100.00
V2S	sec_cm_fsm_sparse	rom_ctrl_sec_cm	2.961m	2.283ms	1	1	100.00
V2S	sec_cm_mem_scramble	rom_ctrl_smoke	6.820s	1.066ms	1	1	100.00
V2S	sec_cm_mem_digest	rom_ctrl_smoke	6.820s	1.066ms	1	1	100.00
V2S	sec_cm_intersig_mubi	rom_ctrl_smoke	6.820s	1.066ms	1	1	100.00
V2S	sec_cm_bus_integrity	rom_ctrl_tl_intg_err	42.170s	1.112ms	1	1	100.00
V2S	sec_cm_bus_local_esc	rom_ctrl_corrupt_sig_fatal_chk	33.440s	568.217us	0	1	0.00
		rom_ctrl_kmac_err_chk	8.510s	1.561ms	1	1	100.00
V2S	sec_cm_mux_mubi	rom_ctrl_corrupt_sig_fatal_chk	33.440s	568.217us	0	1	0.00
V2S	sec_cm_mux_consistency	rom_ctrl_corrupt_sig_fatal_chk	33.440s	568.217us	0	1	0.00
V2S	sec_cm_ctrl_redun	rom_ctrl_corrupt_sig_fatal_chk	33.440s	568.217us	0	1	0.00
V2S	sec_cm_ctrl_mem_integrity	rom_ctrl_passthru_mem_tl_intg_err	20.130s	2.559ms	1	1	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	rom_ctrl_sec_cm	2.961m	2.283ms	1	1	100.00
V2S		TOTAL			3	4	75.00
V3	stress_all_with_rand_reset	rom_ctrl_stress_all_with_rand_reset	51.030s	11.332ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			18	19	94.74

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:695) virtual_sequencer [rom_ctrl_corrupt_sig_fatal_chk_vseq] expect alert:fatal to fire has 1 failures:
  • Test rom_ctrl_corrupt_sig_fatal_chk has 1 failures.

    • 0.rom_ctrl_corrupt_sig_fatal_chk.4436952171907927816443181332560046859284132376159503974454527147951648886019
      Line 96, in log /nightly/runs/scratch/master/rom_ctrl_32kB-sim-vcs/0.rom_ctrl_corrupt_sig_fatal_chk/latest/run.log

        UVM_ERROR @ 568216717 ps: (cip_base_vseq.sv:695) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.rom_ctrl_corrupt_sig_fatal_chk_vseq] expect alert:fatal to fire
        UVM_INFO @ 568216717 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---