RV_TIMER Simulation Results

Thursday May 08 2025 20:26:01 UTC

GitHub Revision: 98096d3

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	random	rv_timer_random	1.920s	12.707us	1	1	100.00
V1	csr_hw_reset	rv_timer_csr_hw_reset	1.560s	54.532us	1	1	100.00
V1	csr_rw	rv_timer_csr_rw	1.790s	25.188us	1	1	100.00
V1	csr_bit_bash	rv_timer_csr_bit_bash	3.470s	86.735us	1	1	100.00
V1	csr_aliasing	rv_timer_csr_aliasing	1.530s	75.506us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	rv_timer_csr_mem_rw_with_rand_reset	1.720s	387.991us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rv_timer_csr_rw	1.790s	25.188us	1	1	100.00
		rv_timer_csr_aliasing	1.530s	75.506us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	random_reset	rv_timer_random_reset	1.540s	233.318us	1	1	100.00
V2	disabled	rv_timer_disabled	1.770s	1.534ms	1	1	100.00
V2	cfg_update_on_fly	rv_timer_cfg_update_on_fly	2.018m	188.148ms	1	1	100.00
V2	no_interrupt_test	rv_timer_cfg_update_on_fly	2.018m	188.148ms	1	1	100.00
V2	stress	rv_timer_stress_all	1.430s	28.275us	1	1	100.00
V2	alert_test	rv_timer_alert_test	1.460s	26.446us	1	1	100.00
V2	intr_test	rv_timer_intr_test	1.490s	15.540us	1	1	100.00
V2	tl_d_oob_addr_access	rv_timer_tl_errors	2.860s	265.816us	1	1	100.00
V2	tl_d_illegal_access	rv_timer_tl_errors	2.860s	265.816us	1	1	100.00
V2	tl_d_outstanding_access	rv_timer_csr_hw_reset	1.560s	54.532us	1	1	100.00
		rv_timer_csr_rw	1.790s	25.188us	1	1	100.00
		rv_timer_csr_aliasing	1.530s	75.506us	1	1	100.00
		rv_timer_same_csr_outstanding	1.540s	14.943us	1	1	100.00
V2	tl_d_partial_access	rv_timer_csr_hw_reset	1.560s	54.532us	1	1	100.00
		rv_timer_csr_rw	1.790s	25.188us	1	1	100.00
		rv_timer_csr_aliasing	1.530s	75.506us	1	1	100.00
		rv_timer_same_csr_outstanding	1.540s	14.943us	1	1	100.00
V2		TOTAL			8	8	100.00
V2S	tl_intg_err	rv_timer_sec_cm	2.180s	168.161us	1	1	100.00
		rv_timer_tl_intg_err	2.230s	617.007us	1	1	100.00
V2S	sec_cm_bus_integrity	rv_timer_tl_intg_err	2.230s	617.007us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	stress_all_with_rand_reset	rv_timer_stress_all_with_rand_reset	25.240s	3.073ms	1	1	100.00
V3		TOTAL			1	1	100.00
	Unmapped tests	rv_timer_min	1.390s	16.179us	1	1	100.00
		rv_timer_max	1.720s	12.746us	1	1	100.00
		TOTAL			19	19	100.00