SPI_DEVICE/1R1W Simulation Results

Thursday May 08 2025 20:26:01 UTC

GitHub Revision: 98096d3

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	1.915m	73.997ms	1	1	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	1.940s	82.305us	1	1	100.00
V1	csr_rw	spi_device_csr_rw	3.330s	534.671us	1	1	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	9.120s	191.595us	1	1	100.00
V1	csr_aliasing	spi_device_csr_aliasing	6.380s	110.930us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	2.470s	179.524us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	3.330s	534.671us	1	1	100.00
		spi_device_csr_aliasing	6.380s	110.930us	1	1	100.00
V1	mem_walk	spi_device_mem_walk	1.590s	10.943us	1	1	100.00
V1	mem_partial_access	spi_device_mem_partial_access	2.510s	103.935us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	csb_read	spi_device_csb_read	1.840s	71.030us	1	1	100.00
V2	mem_parity	spi_device_mem_parity	1.580s	4.763us	0	1	0.00
V2	mem_cfg	spi_device_ram_cfg	1.490s	5.708us	0	1	0.00
V2	tpm_read	spi_device_tpm_rw	2.760s	560.118us	1	1	100.00
V2	tpm_write	spi_device_tpm_rw	2.760s	560.118us	1	1	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	2.950s	408.551us	1	1	100.00
		spi_device_tpm_sts_read	2.010s	233.769us	1	1	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	6.080s	5.348ms	1	1	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	8.220s	4.045ms	1	1	100.00
		spi_device_flash_all	2.355m	33.835ms	1	1	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	23.250s	11.259ms	1	1	100.00
		spi_device_flash_all	2.355m	33.835ms	1	1	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	23.250s	11.259ms	1	1	100.00
		spi_device_flash_all	2.355m	33.835ms	1	1	100.00
V2	cmd_info_slots	spi_device_flash_all	2.355m	33.835ms	1	1	100.00
V2	cmd_read_status	spi_device_intercept	7.590s	1.551ms	1	1	100.00
		spi_device_flash_all	2.355m	33.835ms	1	1	100.00
V2	cmd_read_jedec	spi_device_intercept	7.590s	1.551ms	1	1	100.00
		spi_device_flash_all	2.355m	33.835ms	1	1	100.00
V2	cmd_read_sfdp	spi_device_intercept	7.590s	1.551ms	1	1	100.00
		spi_device_flash_all	2.355m	33.835ms	1	1	100.00
V2	cmd_fast_read	spi_device_intercept	7.590s	1.551ms	1	1	100.00
		spi_device_flash_all	2.355m	33.835ms	1	1	100.00
V2	cmd_read_pipeline	spi_device_intercept	7.590s	1.551ms	1	1	100.00
		spi_device_flash_all	2.355m	33.835ms	1	1	100.00
V2	flash_cmd_upload	spi_device_upload	12.680s	16.712ms	1	1	100.00
V2	mailbox_command	spi_device_mailbox	1.198m	97.057ms	1	1	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	1.198m	97.057ms	1	1	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	1.198m	97.057ms	1	1	100.00
V2	cmd_read_buffer	spi_device_flash_mode	3.920s	694.702us	1	1	100.00
		spi_device_read_buffer_direct	8.090s	1.178ms	1	1	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	1.198m	97.057ms	1	1	100.00
		spi_device_flash_all	2.355m	33.835ms	1	1	100.00
V2	quad_spi	spi_device_flash_all	2.355m	33.835ms	1	1	100.00
V2	dual_spi	spi_device_flash_all	2.355m	33.835ms	1	1	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	2.730s	31.691us	1	1	100.00
V2	write_enable_disable	spi_device_cfg_cmd	2.730s	31.691us	1	1	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	1.915m	73.997ms	1	1	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	1.806m	13.597ms	1	1	100.00
V2	stress_all	spi_device_stress_all	2.349m	107.866ms	1	1	100.00
V2	alert_test	spi_device_alert_test	1.510s	12.794us	1	1	100.00
V2	intr_test	spi_device_intr_test	1.770s	39.904us	1	1	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	3.640s	176.421us	1	1	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	3.640s	176.421us	1	1	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	1.940s	82.305us	1	1	100.00
		spi_device_csr_rw	3.330s	534.671us	1	1	100.00
		spi_device_csr_aliasing	6.380s	110.930us	1	1	100.00
		spi_device_same_csr_outstanding	3.950s	459.792us	1	1	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	1.940s	82.305us	1	1	100.00
		spi_device_csr_rw	3.330s	534.671us	1	1	100.00
		spi_device_csr_aliasing	6.380s	110.930us	1	1	100.00
		spi_device_same_csr_outstanding	3.950s	459.792us	1	1	100.00
V2		TOTAL			20	22	90.91
V2S	tl_intg_err	spi_device_sec_cm	2.240s	1.788ms	1	1	100.00
		spi_device_tl_intg_err	16.290s	2.988ms	1	1	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	16.290s	2.988ms	1	1	100.00
V2S		TOTAL			2	2	100.00
	Unmapped tests	spi_device_flash_mode_ignore_cmds	53.200s	50.773ms	1	1	100.00
		TOTAL			31	33	93.94

Failure Buckets

• UVM_ERROR (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[*]) has 1 failures:

  • Test spi_device_mem_parity has 1 failures.

    • 0.spi_device_mem_parity.76471962853844272937012395807006331934677441016497668764885478367304776218678
      Line 71, in log /nightly/runs/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_mem_parity/latest/run.log

        UVM_ERROR @   4043018 ps: (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[49])
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
        UVM_ERROR @   4043018 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
        UVM_ERROR @   4043018 ps: (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[945])
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
      

• UVM_ERROR (spi_device_ram_cfg_vseq.sv:27) [spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (* [*] vs * [*]) has 1 failures:

  • Test spi_device_ram_cfg has 1 failures.

    • 0.spi_device_ram_cfg.4501843206920327591847284366247817690903280399453399511048102127855999161326
      Line 71, in log /nightly/runs/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_ram_cfg/latest/run.log

        UVM_ERROR @   3474320 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xb0e1d0 [101100001110000111010000] vs 0x0 [0])
        UVM_ERROR @   3570320 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x5dcfe [1011101110011111110] vs 0x0 [0])
        UVM_ERROR @   3603320 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x5bdbfc [10110111101101111111100] vs 0x0 [0])
        UVM_ERROR @   3606320 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x323286 [1100100011001010000110] vs 0x0 [0])
        UVM_ERROR @   3635320 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x8fdb94 [100011111101101110010100] vs 0x0 [0])