SPI_DEVICE/2P Simulation Results

Thursday May 08 2025 20:26:01 UTC

GitHub Revision: 98096d3

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	1.997m	79.158ms	1	1	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	1.630s	45.900us	1	1	100.00
V1	csr_rw	spi_device_csr_rw	2.330s	29.589us	1	1	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	23.320s	528.472us	1	1	100.00
V1	csr_aliasing	spi_device_csr_aliasing	6.610s	406.538us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	3.660s	42.158us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	2.330s	29.589us	1	1	100.00
		spi_device_csr_aliasing	6.610s	406.538us	1	1	100.00
V1	mem_walk	spi_device_mem_walk	1.510s	10.230us	1	1	100.00
V1	mem_partial_access	spi_device_mem_partial_access	2.800s	48.244us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	csb_read	spi_device_csb_read	1.730s	73.054us	1	1	100.00
V2	mem_parity	spi_device_mem_parity	1.880s	54.172us	1	1	100.00
V2	mem_cfg	spi_device_ram_cfg	1.540s	17.489us	1	1	100.00
V2	tpm_read	spi_device_tpm_rw	1.920s	48.895us	1	1	100.00
V2	tpm_write	spi_device_tpm_rw	1.920s	48.895us	1	1	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	5.110s	3.466ms	1	1	100.00
		spi_device_tpm_sts_read	1.920s	115.471us	1	1	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	23.820s	6.406ms	1	1	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	9.650s	3.751ms	1	1	100.00
		spi_device_flash_all	37.350s	15.814ms	0	1	0.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	18.840s	25.396ms	1	1	100.00
		spi_device_flash_all	37.350s	15.814ms	0	1	0.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	18.840s	25.396ms	1	1	100.00
		spi_device_flash_all	37.350s	15.814ms	0	1	0.00
V2	cmd_info_slots	spi_device_flash_all	37.350s	15.814ms	0	1	0.00
V2	cmd_read_status	spi_device_intercept	6.670s	2.728ms	1	1	100.00
		spi_device_flash_all	37.350s	15.814ms	0	1	0.00
V2	cmd_read_jedec	spi_device_intercept	6.670s	2.728ms	1	1	100.00
		spi_device_flash_all	37.350s	15.814ms	0	1	0.00
V2	cmd_read_sfdp	spi_device_intercept	6.670s	2.728ms	1	1	100.00
		spi_device_flash_all	37.350s	15.814ms	0	1	0.00
V2	cmd_fast_read	spi_device_intercept	6.670s	2.728ms	1	1	100.00
		spi_device_flash_all	37.350s	15.814ms	0	1	0.00
V2	cmd_read_pipeline	spi_device_intercept	6.670s	2.728ms	1	1	100.00
		spi_device_flash_all	37.350s	15.814ms	0	1	0.00
V2	flash_cmd_upload	spi_device_upload	8.540s	5.314ms	1	1	100.00
V2	mailbox_command	spi_device_mailbox	2.560s	122.268us	1	1	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	2.560s	122.268us	1	1	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	2.560s	122.268us	1	1	100.00
V2	cmd_read_buffer	spi_device_flash_mode	6.480s	483.691us	1	1	100.00
		spi_device_read_buffer_direct	3.970s	320.596us	1	1	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	2.560s	122.268us	1	1	100.00
		spi_device_flash_all	37.350s	15.814ms	0	1	0.00
V2	quad_spi	spi_device_flash_all	37.350s	15.814ms	0	1	0.00
V2	dual_spi	spi_device_flash_all	37.350s	15.814ms	0	1	0.00
V2	4b_3b_feature	spi_device_cfg_cmd	4.000s	884.441us	1	1	100.00
V2	write_enable_disable	spi_device_cfg_cmd	4.000s	884.441us	1	1	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	1.997m	79.158ms	1	1	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	42.000s	8.246ms	1	1	100.00
V2	stress_all	spi_device_stress_all	4.163m	180.748ms	1	1	100.00
V2	alert_test	spi_device_alert_test	1.890s	19.218us	1	1	100.00
V2	intr_test	spi_device_intr_test	1.680s	72.209us	1	1	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	2.650s	75.837us	1	1	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	2.650s	75.837us	1	1	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	1.630s	45.900us	1	1	100.00
		spi_device_csr_rw	2.330s	29.589us	1	1	100.00
		spi_device_csr_aliasing	6.610s	406.538us	1	1	100.00
		spi_device_same_csr_outstanding	2.920s	151.621us	1	1	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	1.630s	45.900us	1	1	100.00
		spi_device_csr_rw	2.330s	29.589us	1	1	100.00
		spi_device_csr_aliasing	6.610s	406.538us	1	1	100.00
		spi_device_same_csr_outstanding	2.920s	151.621us	1	1	100.00
V2		TOTAL			21	22	95.45
V2S	tl_intg_err	spi_device_sec_cm	1.910s	183.550us	1	1	100.00
		spi_device_tl_intg_err	9.990s	1.017ms	1	1	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	9.990s	1.017ms	1	1	100.00
V2S		TOTAL			2	2	100.00
	Unmapped tests	spi_device_flash_mode_ignore_cmds	2.040s	589.416us	1	1	100.00
		TOTAL			32	33	96.97

Failure Buckets

• UVM_ERROR (spi_device_scoreboard.sv:1115) [scoreboard] Check failed rtl_addr_4b_en == tl_ul_side_addr_mode_addr_4b_en (* [*] vs * [*]) ADDR_MODE.addr_4b_en Comparison mismatch, act (*) != exp * has 1 failures:
  • Test spi_device_flash_all has 1 failures.

    • 0.spi_device_flash_all.16199411064001575763001806202719084340274454245384125519694238843764066274752
      Line 72, in log /nightly/runs/scratch/master/spi_device_2p-sim-vcs/0.spi_device_flash_all/latest/run.log

        UVM_ERROR @ 547841871 ps: (spi_device_scoreboard.sv:1115) [uvm_test_top.env.scoreboard] Check failed rtl_addr_4b_en == tl_ul_side_addr_mode_addr_4b_en (1 [0x1] vs 0 [0x0]) ADDR_MODE.addr_4b_en Comparison mismatch, act (0x1) != exp 0
        tl_ul_fuzzy_flash_status_q[i] = 0x0
        tl_ul_fuzzy_flash_status_q[i] = 0x831380
        UVM_INFO @ 1735816138 ps: (spi_device_flash_all_vseq.sv:72) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_all_vseq] spi_device_env_pkg::\spi_device_flash_all_vseq::main_seq .unnamed$$_0 - END:running iteration 0/12
        UVM_INFO @ 1735816138 ps: (spi_device_flash_all_vseq.sv:51) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_all_vseq] spi_device_env_pkg::\spi_device_flash_all_vseq::main_seq .unnamed$$_0 - running iteration 1/12