SPI_HOST Simulation Results

Thursday May 08 2025 20:26:01 UTC

GitHub Revision: 98096d3

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_host_smoke	1.067m	2.004ms	1	1	100.00
V1	csr_hw_reset	spi_host_csr_hw_reset	4.000s	50.464us	1	1	100.00
V1	csr_rw	spi_host_csr_rw	4.000s	36.253us	1	1	100.00
V1	csr_bit_bash	spi_host_csr_bit_bash	5.000s	244.808us	1	1	100.00
V1	csr_aliasing	spi_host_csr_aliasing	3.000s	31.377us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	spi_host_csr_mem_rw_with_rand_reset	4.000s	87.409us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_host_csr_rw	4.000s	36.253us	1	1	100.00
		spi_host_csr_aliasing	3.000s	31.377us	1	1	100.00
V1	mem_walk	spi_host_mem_walk	4.000s	22.237us	1	1	100.00
V1	mem_partial_access	spi_host_mem_partial_access	5.000s	21.275us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	performance	spi_host_performance	4.000s	19.391us	1	1	100.00
V2	error_event_intr	spi_host_overflow_underflow	5.000s	57.061us	1	1	100.00
		spi_host_error_cmd	4.000s	127.170us	1	1	100.00
		spi_host_event	16.000s	517.618us	1	1	100.00
V2	clock_rate	spi_host_speed	7.000s	183.796us	1	1	100.00
V2	speed	spi_host_speed	7.000s	183.796us	1	1	100.00
V2	chip_select_timing	spi_host_speed	7.000s	183.796us	1	1	100.00
V2	sw_reset	spi_host_sw_reset	6.000s	324.946us	1	1	100.00
V2	passthrough_mode	spi_host_passthrough_mode	4.000s	132.183us	1	1	100.00
V2	cpol_cpha	spi_host_speed	7.000s	183.796us	1	1	100.00
V2	full_cycle	spi_host_speed	7.000s	183.796us	1	1	100.00
V2	duplex	spi_host_smoke	1.067m	2.004ms	1	1	100.00
V2	tx_rx_only	spi_host_smoke	1.067m	2.004ms	1	1	100.00
V2	stress_all	spi_host_stress_all	5.000s	73.000us	1	1	100.00
V2	spien	spi_host_spien	5.000s	1.330ms	1	1	100.00
V2	stall	spi_host_status_stall	23.200m	144.403ms	1	1	100.00
V2	Idlecsbactive	spi_host_idlecsbactive	4.000s	133.346us	1	1	100.00
V2	data_fifo_status	spi_host_overflow_underflow	5.000s	57.061us	1	1	100.00
V2	alert_test	spi_host_alert_test	4.000s	43.734us	1	1	100.00
V2	intr_test	spi_host_intr_test	4.000s	40.591us	1	1	100.00
V2	tl_d_oob_addr_access	spi_host_tl_errors	5.000s	124.895us	1	1	100.00
V2	tl_d_illegal_access	spi_host_tl_errors	5.000s	124.895us	1	1	100.00
V2	tl_d_outstanding_access	spi_host_csr_hw_reset	4.000s	50.464us	1	1	100.00
		spi_host_csr_rw	4.000s	36.253us	1	1	100.00
		spi_host_csr_aliasing	3.000s	31.377us	1	1	100.00
		spi_host_same_csr_outstanding	4.000s	109.782us	1	1	100.00
V2	tl_d_partial_access	spi_host_csr_hw_reset	4.000s	50.464us	1	1	100.00
		spi_host_csr_rw	4.000s	36.253us	1	1	100.00
		spi_host_csr_aliasing	3.000s	31.377us	1	1	100.00
		spi_host_same_csr_outstanding	4.000s	109.782us	1	1	100.00
V2		TOTAL			15	15	100.00
V2S	tl_intg_err	spi_host_tl_intg_err	4.000s	1.303ms	1	1	100.00
		spi_host_sec_cm	4.000s	301.529us	1	1	100.00
V2S	sec_cm_bus_integrity	spi_host_tl_intg_err	4.000s	1.303ms	1	1	100.00
V2S		TOTAL			2	2	100.00
	Unmapped tests	spi_host_upper_range_clkdiv	6.550m	59.897ms	1	1	100.00
		TOTAL			26	26	100.00