SRAM_CTRL/MAIN Simulation Results

Thursday May 08 2025 20:26:01 UTC

GitHub Revision: 98096d3

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	47.800s	5.571ms	1	1	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	1.530s	19.455us	1	1	100.00
V1	csr_rw	sram_ctrl_csr_rw	1.530s	25.310us	1	1	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	2.530s	479.505us	1	1	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	1.560s	19.848us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	3.270s	1.363ms	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	1.530s	25.310us	1	1	100.00
		sram_ctrl_csr_aliasing	1.560s	19.848us	1	1	100.00
V1	mem_walk	sram_ctrl_mem_walk	3.537m	5.535ms	1	1	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	1.897m	24.604ms	1	1	100.00
V1		TOTAL			8	8	100.00
V2	multiple_keys	sram_ctrl_multiple_keys	7.396m	14.822ms	1	1	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	2.123m	12.228ms	1	1	100.00
V2	bijection	sram_ctrl_bijection	17.942m	67.695ms	1	1	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	4.534m	6.917ms	1	1	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	1.309m	97.289ms	1	1	100.00
V2	executable	sram_ctrl_executable	41.060s	1.295ms	1	1	100.00
V2	partial_access	sram_ctrl_partial_access	4.750s	422.847us	1	1	100.00
		sram_ctrl_partial_access_b2b	4.731m	63.237ms	1	1	100.00
V2	max_throughput	sram_ctrl_max_throughput	55.150s	791.694us	1	1	100.00
		sram_ctrl_throughput_w_partial_write	17.980s	772.213us	1	1	100.00
		sram_ctrl_throughput_w_readback	28.540s	2.084ms	1	1	100.00
V2	regwen	sram_ctrl_regwen	12.296m	8.665ms	1	1	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	3.340s	854.073us	1	1	100.00
V2	stress_all	sram_ctrl_stress_all	38.030m	63.243ms	1	1	100.00
V2	alert_test	sram_ctrl_alert_test	1.570s	36.593us	1	1	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	3.160s	33.997us	1	1	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	3.160s	33.997us	1	1	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	1.530s	19.455us	1	1	100.00
		sram_ctrl_csr_rw	1.530s	25.310us	1	1	100.00
		sram_ctrl_csr_aliasing	1.560s	19.848us	1	1	100.00
		sram_ctrl_same_csr_outstanding	1.570s	36.795us	1	1	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	1.530s	19.455us	1	1	100.00
		sram_ctrl_csr_rw	1.530s	25.310us	1	1	100.00
		sram_ctrl_csr_aliasing	1.560s	19.848us	1	1	100.00
		sram_ctrl_same_csr_outstanding	1.570s	36.795us	1	1	100.00
V2		TOTAL			17	17	100.00
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	18.580s	16.074ms	1	1	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	1.540s	66.519us	0	1	0.00
		sram_ctrl_tl_intg_err	2.100s	600.013us	1	1	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	1.540s	66.519us	0	1	0.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	2.100s	600.013us	1	1	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	12.296m	8.665ms	1	1	100.00
V2S	sec_cm_readback_config_regwen	sram_ctrl_regwen	12.296m	8.665ms	1	1	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	1.530s	25.310us	1	1	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	41.060s	1.295ms	1	1	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	41.060s	1.295ms	1	1	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	41.060s	1.295ms	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	1.309m	97.289ms	1	1	100.00
V2S	sec_cm_prim_ram_ctrl_mubi	sram_ctrl_mubi_enc_err	5.870s	1.554ms	1	1	100.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	18.580s	16.074ms	1	1	100.00
V2S	sec_cm_mem_readback	sram_ctrl_readback_err	5.180s	2.646ms	1	1	100.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	47.800s	5.571ms	1	1	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	47.800s	5.571ms	1	1	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	41.060s	1.295ms	1	1	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	1.540s	66.519us	0	1	0.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	1.309m	97.289ms	1	1	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	1.540s	66.519us	0	1	0.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	1.540s	66.519us	0	1	0.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	47.800s	5.571ms	1	1	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	1.540s	66.519us	0	1	0.00
V2S		TOTAL			4	5	80.00
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	10.150s	792.791us	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			30	31	96.77

Failure Buckets

• UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: * has 1 failures:
  • Test sram_ctrl_sec_cm has 1 failures.

    • 0.sram_ctrl_sec_cm.41114295615472506525164701839921975318065049887044888871398355665335773284511
      Line 98, in log /nightly/runs/scratch/master/sram_ctrl_main-sim-vcs/0.sram_ctrl_sec_cm/latest/run.log

        UVM_ERROR @  66519405 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
        UVM_INFO @  66519405 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---