SRAM_CTRL/RET Simulation Results

Thursday May 08 2025 20:26:01 UTC

GitHub Revision: 98096d3

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	8.620s	1.178ms	1	1	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	1.690s	19.580us	1	1	100.00
V1	csr_rw	sram_ctrl_csr_rw	1.610s	43.962us	1	1	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	2.090s	232.060us	1	1	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	1.670s	79.341us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	2.420s	133.812us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	1.610s	43.962us	1	1	100.00
		sram_ctrl_csr_aliasing	1.670s	79.341us	1	1	100.00
V1	mem_walk	sram_ctrl_mem_walk	5.310s	240.064us	1	1	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	3.220s	102.705us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	multiple_keys	sram_ctrl_multiple_keys	8.102m	63.351ms	1	1	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	4.420m	16.598ms	1	1	100.00
V2	bijection	sram_ctrl_bijection	25.190s	3.784ms	1	1	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	6.029m	2.539ms	1	1	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	3.770s	430.338us	1	1	100.00
V2	executable	sram_ctrl_executable	5.285m	2.677ms	1	1	100.00
V2	partial_access	sram_ctrl_partial_access	3.260s	1.271ms	1	1	100.00
		sram_ctrl_partial_access_b2b	5.909m	79.530ms	1	1	100.00
V2	max_throughput	sram_ctrl_max_throughput	7.210s	71.190us	1	1	100.00
		sram_ctrl_throughput_w_partial_write	2.130s	163.757us	1	1	100.00
		sram_ctrl_throughput_w_readback	38.870s	603.818us	1	1	100.00
V2	regwen	sram_ctrl_regwen	4.990m	27.175ms	1	1	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	1.580s	33.405us	1	1	100.00
V2	stress_all	sram_ctrl_stress_all	31.461m	45.404ms	1	1	100.00
V2	alert_test	sram_ctrl_alert_test	1.560s	14.129us	1	1	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	4.220s	588.022us	1	1	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	4.220s	588.022us	1	1	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	1.690s	19.580us	1	1	100.00
		sram_ctrl_csr_rw	1.610s	43.962us	1	1	100.00
		sram_ctrl_csr_aliasing	1.670s	79.341us	1	1	100.00
		sram_ctrl_same_csr_outstanding	1.710s	26.862us	1	1	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	1.690s	19.580us	1	1	100.00
		sram_ctrl_csr_rw	1.610s	43.962us	1	1	100.00
		sram_ctrl_csr_aliasing	1.670s	79.341us	1	1	100.00
		sram_ctrl_same_csr_outstanding	1.710s	26.862us	1	1	100.00
V2		TOTAL			17	17	100.00
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	3.240s	1.020ms	1	1	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	1.450s	9.748us	0	1	0.00
		sram_ctrl_tl_intg_err	2.250s	513.226us	1	1	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	1.450s	9.748us	0	1	0.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	2.250s	513.226us	1	1	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	4.990m	27.175ms	1	1	100.00
V2S	sec_cm_readback_config_regwen	sram_ctrl_regwen	4.990m	27.175ms	1	1	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	1.610s	43.962us	1	1	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	5.285m	2.677ms	1	1	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	5.285m	2.677ms	1	1	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	5.285m	2.677ms	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	3.770s	430.338us	1	1	100.00
V2S	sec_cm_prim_ram_ctrl_mubi	sram_ctrl_mubi_enc_err	1.840s	62.975us	1	1	100.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	3.240s	1.020ms	1	1	100.00
V2S	sec_cm_mem_readback	sram_ctrl_readback_err	1.810s	192.832us	1	1	100.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	8.620s	1.178ms	1	1	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	8.620s	1.178ms	1	1	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	5.285m	2.677ms	1	1	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	1.450s	9.748us	0	1	0.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	3.770s	430.338us	1	1	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	1.450s	9.748us	0	1	0.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	1.450s	9.748us	0	1	0.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	8.620s	1.178ms	1	1	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	1.450s	9.748us	0	1	0.00
V2S		TOTAL			4	5	80.00
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	27.680s	985.948us	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			30	31	96.77

Failure Buckets

• Offending '(!$isunknown(rdata_o))' has 1 failures:
  • Test sram_ctrl_sec_cm has 1 failures.

    • 0.sram_ctrl_sec_cm.45887588509568820338580776217306419841498721103109752035471075783238450214843
      Line 94, in log /nightly/runs/scratch/master/sram_ctrl_ret-sim-vcs/0.sram_ctrl_sec_cm/latest/run.log

            Offending '(!$isunknown(rdata_o))'
        UVM_ERROR @   9748142 ps: (prim_fifo_sync.sv:218) [ASSERT FAILED] DataKnown_A
        UVM_INFO @   9748142 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---