SYSRST_CTRL Simulation Results

Thursday May 08 2025 20:26:01 UTC

GitHub Revision: `98096d3`

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sysrst_ctrl_smoke	5.650s	2.112ms	1	1	100.00
V1	input_output_inverted	sysrst_ctrl_in_out_inverted	3.940s	2.479ms	1	1	100.00
V1	combo_detect_ec_rst	sysrst_ctrl_combo_detect_ec_rst	3.950s	2.398ms	0	1	0.00
V1	combo_detect_ec_rst_with_pre_cond	sysrst_ctrl_combo_detect_ec_rst_with_pre_cond	3.800s	2.320ms	1	1	100.00
V1	csr_hw_reset	sysrst_ctrl_csr_hw_reset	2.300s	4.128ms	1	1	100.00
V1	csr_rw	sysrst_ctrl_csr_rw	7.610s	2.053ms	1	1	100.00
V1	csr_bit_bash	sysrst_ctrl_csr_bit_bash	38.690s	38.198ms	1	1	100.00
V1	csr_aliasing	sysrst_ctrl_csr_aliasing	3.800s	2.263ms	1	1	100.00
V1	csr_mem_rw_with_rand_reset	sysrst_ctrl_csr_mem_rw_with_rand_reset	2.860s	2.166ms	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sysrst_ctrl_csr_rw	7.610s	2.053ms	1	1	100.00
		sysrst_ctrl_csr_aliasing	3.800s	2.263ms	1	1	100.00
V1		TOTAL			8	9	88.89
V2	combo_detect	sysrst_ctrl_combo_detect	1.042m	69.656ms	1	1	100.00
V2	combo_detect_with_pre_cond	sysrst_ctrl_combo_detect_with_pre_cond	6.228m	208.485ms	1	1	100.00
V2	auto_block_key_outputs	sysrst_ctrl_auto_blk_key_output	11.680s	3.241ms	1	1	100.00
V2	keyboard_input_triggered_interrupt	sysrst_ctrl_edge_detect	10.860s	2.768ms	1	1	100.00
V2	pin_output_keyboard_inversion_control	sysrst_ctrl_pin_override_test	2.810s	2.549ms	1	1	100.00
V2	pin_input_value_accessibility	sysrst_ctrl_pin_access_test	4.670s	2.198ms	1	1	100.00
V2	ec_power_on_reset	sysrst_ctrl_ec_pwr_on_rst	10.160s	3.665ms	1	1	100.00
V2	flash_write_protect_output	sysrst_ctrl_flash_wr_prot_out	7.950s	2.612ms	1	1	100.00
V2	ultra_low_power_test	sysrst_ctrl_ultra_low_pwr	3.860s	8.220ms	1	1	100.00
V2	sysrst_ctrl_feature_disable	sysrst_ctrl_feature_disable	1.387m	41.997ms	0	1	0.00
V2	stress_all	sysrst_ctrl_stress_all	13.110s	11.559ms	1	1	100.00
V2	alert_test	sysrst_ctrl_alert_test	2.810s	2.027ms	1	1	100.00
V2	intr_test	sysrst_ctrl_intr_test	4.700s	2.014ms	1	1	100.00
V2	tl_d_oob_addr_access	sysrst_ctrl_tl_errors	4.260s	2.330ms	1	1	100.00
V2	tl_d_illegal_access	sysrst_ctrl_tl_errors	4.260s	2.330ms	1	1	100.00
V2	tl_d_outstanding_access	sysrst_ctrl_csr_hw_reset	2.300s	4.128ms	1	1	100.00
		sysrst_ctrl_csr_rw	7.610s	2.053ms	1	1	100.00
		sysrst_ctrl_csr_aliasing	3.800s	2.263ms	1	1	100.00
		sysrst_ctrl_same_csr_outstanding	4.800s	8.018ms	1	1	100.00
V2	tl_d_partial_access	sysrst_ctrl_csr_hw_reset	2.300s	4.128ms	1	1	100.00
		sysrst_ctrl_csr_rw	7.610s	2.053ms	1	1	100.00
		sysrst_ctrl_csr_aliasing	3.800s	2.263ms	1	1	100.00
		sysrst_ctrl_same_csr_outstanding	4.800s	8.018ms	1	1	100.00
V2		TOTAL			14	15	93.33
V2S	tl_intg_err	sysrst_ctrl_sec_cm	25.400s	22.015ms	1	1	100.00
		sysrst_ctrl_tl_intg_err	43.440s	22.258ms	1	1	100.00
V2S	sec_cm_bus_integrity	sysrst_ctrl_tl_intg_err	43.440s	22.258ms	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	stress_all_with_rand_reset	sysrst_ctrl_stress_all_with_rand_reset	11.430s	7.767ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			25	27	92.59

Failure Buckets

UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: sysrst_ctrl_reg_block.combo_intr_status reset value: * has 1 failures:
- Test sysrst_ctrl_combo_detect_ec_rst has 1 failures.
  - 0.sysrst_ctrl_combo_detect_ec_rst.72302576324046683891253454843514373225885473656306541832023899048616727991042
    Line 380, in log /nightly/runs/scratch/master/sysrst_ctrl-sim-vcs/0.sysrst_ctrl_combo_detect_ec_rst/latest/run.log
```
  UVM_ERROR @ 2180711466 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sysrst_ctrl_reg_block.combo_intr_status reset value: 0x0
  UVM_INFO @ 2398131466 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR (cip_base_scoreboard.sv:251) scoreboard [scoreboard] alert fatal_fault has unexpected timeout error has 1 failures:

Test sysrst_ctrl_feature_disable has 1 failures.

0.sysrst_ctrl_feature_disable.65636743799392261765256539089049088279843293653091620928800227602274304193671
Line 409, in log /nightly/runs/scratch/master/sysrst_ctrl-sim-vcs/0.sysrst_ctrl_feature_disable/latest/run.log

  UVM_ERROR @ 41996680019 ps: (cip_base_scoreboard.sv:251) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault has unexpected timeout error
  UVM_ERROR @ 41996710630 ps: (cip_base_scoreboard.sv:263) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_fault triggered unexpectedly
  UVM_INFO @ 41996710630 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---