UART Simulation Results

Thursday May 08 2025 20:26:01 UTC

GitHub Revision: 98096d3

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	uart_smoke	2.730s	743.031us	1	1	100.00
V1	csr_hw_reset	uart_csr_hw_reset	1.450s	32.956us	1	1	100.00
V1	csr_rw	uart_csr_rw	1.920s	11.422us	1	1	100.00
V1	csr_bit_bash	uart_csr_bit_bash	2.910s	504.530us	1	1	100.00
V1	csr_aliasing	uart_csr_aliasing	1.650s	21.204us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	uart_csr_mem_rw_with_rand_reset	1.760s	43.476us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	uart_csr_rw	1.920s	11.422us	1	1	100.00
		uart_csr_aliasing	1.650s	21.204us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	base_random_seq	uart_tx_rx	27.790s	90.954ms	1	1	100.00
V2	parity	uart_smoke	2.730s	743.031us	1	1	100.00
		uart_tx_rx	27.790s	90.954ms	1	1	100.00
V2	parity_error	uart_intr	22.970s	81.635ms	1	1	100.00
		uart_rx_parity_err	38.360s	34.194ms	1	1	100.00
V2	watermark	uart_tx_rx	27.790s	90.954ms	1	1	100.00
		uart_intr	22.970s	81.635ms	1	1	100.00
V2	fifo_full	uart_fifo_full	7.691m	245.388ms	1	1	100.00
V2	fifo_overflow	uart_fifo_overflow	1.333m	267.027ms	1	1	100.00
V2	fifo_reset	uart_fifo_reset	24.270s	20.985ms	1	1	100.00
V2	rx_frame_err	uart_intr	22.970s	81.635ms	1	1	100.00
V2	rx_break_err	uart_intr	22.970s	81.635ms	1	1	100.00
V2	rx_timeout	uart_intr	22.970s	81.635ms	1	1	100.00
V2	perf	uart_perf	3.070m	7.777ms	1	1	100.00
V2	sys_loopback	uart_loopback	2.730s	1.325ms	1	1	100.00
V2	line_loopback	uart_loopback	2.730s	1.325ms	1	1	100.00
V2	rx_noise_filter	uart_noise_filter	14.130s	8.436ms	1	1	100.00
V2	rx_start_bit_filter	uart_rx_start_bit_filter	4.720s	4.445ms	1	1	100.00
V2	tx_overide	uart_tx_ovrd	3.220s	854.219us	1	1	100.00
V2	rx_oversample	uart_rx_oversample	2.000s	1.305ms	1	1	100.00
V2	long_b2b_transfer	uart_long_xfer_wo_dly	6.997m	121.188ms	1	1	100.00
V2	stress_all	uart_stress_all	2.318m	115.834ms	1	1	100.00
V2	alert_test	uart_alert_test	1.480s	15.477us	1	1	100.00
V2	intr_test	uart_intr_test	1.410s	35.810us	1	1	100.00
V2	tl_d_oob_addr_access	uart_tl_errors	1.960s	30.270us	1	1	100.00
V2	tl_d_illegal_access	uart_tl_errors	1.960s	30.270us	1	1	100.00
V2	tl_d_outstanding_access	uart_csr_hw_reset	1.450s	32.956us	1	1	100.00
		uart_csr_rw	1.920s	11.422us	1	1	100.00
		uart_csr_aliasing	1.650s	21.204us	1	1	100.00
		uart_same_csr_outstanding	1.540s	22.689us	1	1	100.00
V2	tl_d_partial_access	uart_csr_hw_reset	1.450s	32.956us	1	1	100.00
		uart_csr_rw	1.920s	11.422us	1	1	100.00
		uart_csr_aliasing	1.650s	21.204us	1	1	100.00
		uart_same_csr_outstanding	1.540s	22.689us	1	1	100.00
V2		TOTAL			18	18	100.00
V2S	tl_intg_err	uart_sec_cm	1.870s	142.218us	1	1	100.00
		uart_tl_intg_err	2.430s	78.069us	1	1	100.00
V2S	sec_cm_bus_integrity	uart_tl_intg_err	2.430s	78.069us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	stress_all_with_rand_reset	uart_stress_all_with_rand_reset	12.810s	5.862ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			27	27	100.00