CHIP Simulation Results

Thursday May 08 2025 20:26:01 UTC

GitHub Revision: `98096d3`

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	chip_sw_example_tests	chip_sw_example_flash	2.188m	2.530ms	1	1	100.00
		chip_sw_example_rom	1.081m	1.849ms	1	1	100.00
		chip_sw_example_manufacturer	2.188m	3.177ms	1	1	100.00
		chip_sw_example_concurrency	2.242m	3.197ms	1	1	100.00
V1	csr_hw_reset	chip_csr_hw_reset	3.614m	7.487ms	1	1	100.00
V1	csr_rw	chip_csr_rw	2.811m	3.818ms	1	1	100.00
V1	csr_bit_bash	chip_csr_bit_bash	52.947m	42.262ms	1	1	100.00
V1	csr_aliasing	chip_csr_aliasing	1.168h	35.385ms	1	1	100.00
V1	csr_mem_rw_with_rand_reset	chip_csr_mem_rw_with_rand_reset	50.180s	2.171ms	0	1	0.00
V1	regwen_csr_and_corresponding_lockable_csr	chip_csr_aliasing	1.168h	35.385ms	1	1	100.00
		chip_csr_rw	2.811m	3.818ms	1	1	100.00
V1	xbar_smoke	xbar_smoke	5.580s	50.915us	1	1	100.00
V1	chip_sw_gpio_out	chip_sw_gpio	4.796m	4.047ms	1	1	100.00
V1	chip_sw_gpio_in	chip_sw_gpio	4.796m	4.047ms	1	1	100.00
V1	chip_sw_gpio_irq	chip_sw_gpio	4.796m	4.047ms	1	1	100.00
V1	chip_sw_uart_tx_rx	chip_sw_uart_tx_rx	5.328m	4.751ms	1	1	100.00
V1	chip_sw_uart_rx_overflow	chip_sw_uart_tx_rx	5.328m	4.751ms	1	1	100.00
		chip_sw_uart_tx_rx_idx1	5.824m	3.388ms	1	1	100.00
		chip_sw_uart_tx_rx_idx2	6.028m	4.240ms	1	1	100.00
		chip_sw_uart_tx_rx_idx3	5.740m	3.527ms	1	1	100.00
V1	chip_sw_uart_baud_rate	chip_sw_uart_rand_baudrate	6.351m	4.254ms	1	1	100.00
V1	chip_sw_uart_tx_rx_alt_clk_freq	chip_sw_uart_tx_rx_alt_clk_freq	15.637m	8.770ms	1	1	100.00
		chip_sw_uart_tx_rx_alt_clk_freq_low_speed	9.595m	7.809ms	1	1	100.00
V1		TOTAL			17	18	94.44
V2	chip_pin_mux	chip_padctrl_attributes	2.747m	5.262ms	1	1	100.00
V2	chip_padctrl_attributes	chip_padctrl_attributes	2.747m	5.262ms	1	1	100.00
V2	chip_sw_sleep_pin_mio_dio_val	chip_sw_sleep_pin_mio_dio_val	3.123m	3.000ms	0	1	0.00
V2	chip_sw_sleep_pin_wake	chip_sw_sleep_pin_wake	2.656m	3.392ms	1	1	100.00
V2	chip_sw_sleep_pin_retention	chip_sw_sleep_pin_retention	3.284m	3.546ms	1	1	100.00
V2	chip_sw_tap_strap_sampling	chip_tap_straps_dev	6.156m	6.992ms	1	1	100.00
		chip_tap_straps_testunlock0	1.764m	3.238ms	1	1	100.00
		chip_tap_straps_rma	2.081m	3.487ms	1	1	100.00
		chip_tap_straps_prod	18.589m	17.903ms	1	1	100.00
V2	chip_sw_pattgen_ios	chip_sw_pattgen_ios	2.071m	3.138ms	1	1	100.00
V2	chip_sw_sleep_pwm_pulses	chip_sw_sleep_pwm_pulses	12.309m	9.191ms	1	1	100.00
V2	chip_sw_data_integrity	chip_sw_data_integrity_escalation	6.174m	5.718ms	1	1	100.00
V2	chip_sw_instruction_integrity	chip_sw_data_integrity_escalation	6.174m	5.718ms	1	1	100.00
V2	chip_sw_ast_clk_outputs	chip_sw_ast_clk_outputs	9.093m	8.322ms	1	1	100.00
V2	chip_sw_ast_clk_rst_inputs	chip_sw_ast_clk_rst_inputs	16.646m	14.131ms	0	1	0.00
V2	chip_sw_ast_sys_clk_jitter	chip_sw_flash_ctrl_ops_jitter_en	5.786m	3.918ms	1	1	100.00
		chip_sw_flash_ctrl_access_jitter_en	10.319m	6.702ms	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	52.687m	18.497ms	1	1	100.00
		chip_sw_aes_enc_jitter_en	2.124m	2.539ms	1	1	100.00
		chip_sw_edn_entropy_reqs_jitter	10.893m	6.549ms	1	1	100.00
		chip_sw_hmac_enc_jitter_en	2.779m	2.841ms	1	1	100.00
		chip_sw_keymgr_key_derivation_jitter_en	9.370m	6.450ms	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en	2.434m	2.954ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	5.152m	4.096ms	1	1	100.00
		chip_sw_clkmgr_jitter	3.111m	2.656ms	1	1	100.00
V2	chip_sw_ast_usb_clk_calib	chip_sw_usb_ast_clk_calib	2.877m	3.776ms	1	1	100.00
V2	chip_sw_sensor_ctrl_ast_alerts	chip_sw_sensor_ctrl_alert	10.080m	9.234ms	1	1	100.00
		chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	3.895m	5.176ms	1	1	100.00
V2	chip_sw_sensor_ctrl_ast_status	chip_sw_sensor_ctrl_status	2.258m	2.785ms	1	1	100.00
V2	chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	3.895m	5.176ms	1	1	100.00
V2	chip_sw_smoketest	chip_sw_flash_scrambling_smoketest	2.168m	2.266ms	1	1	100.00
		chip_sw_aes_smoketest	3.129m	3.098ms	1	1	100.00
		chip_sw_aon_timer_smoketest	2.763m	3.178ms	1	1	100.00
		chip_sw_clkmgr_smoketest	1.775m	2.250ms	1	1	100.00
		chip_sw_csrng_smoketest	2.198m	2.702ms	1	1	100.00
		chip_sw_entropy_src_smoketest	4.936m	4.109ms	1	1	100.00
		chip_sw_gpio_smoketest	2.642m	3.282ms	1	1	100.00
		chip_sw_hmac_smoketest	2.985m	2.975ms	1	1	100.00
		chip_sw_kmac_smoketest	3.023m	2.590ms	1	1	100.00
		chip_sw_otbn_smoketest	15.845m	8.841ms	1	1	100.00
		chip_sw_pwrmgr_smoketest	5.016m	6.687ms	1	1	100.00
		chip_sw_pwrmgr_usbdev_smoketest	2.833m	5.816ms	1	1	100.00
		chip_sw_rv_plic_smoketest	1.997m	2.413ms	1	1	100.00
		chip_sw_rv_timer_smoketest	1.938m	2.486ms	1	1	100.00
		chip_sw_rstmgr_smoketest	1.777m	3.036ms	1	1	100.00
		chip_sw_sram_ctrl_smoketest	2.182m	2.676ms	1	1	100.00
		chip_sw_uart_smoketest	1.898m	3.359ms	1	1	100.00
V2	chip_sw_otp_smoketest	chip_sw_otp_ctrl_smoketest	2.012m	2.271ms	1	1	100.00
V2	chip_sw_rom_functests	rom_keymgr_functest	4.416m	3.921ms	1	1	100.00
V2	chip_sw_boot	chip_sw_uart_tx_rx_bootstrap	2.030h	60.509ms	1	1	100.00
V2	chip_sw_secure_boot	rom_e2e_smoke	40.168m	14.300ms	1	1	100.00
V2	chip_sw_rom_raw_unlock	rom_raw_unlock	2.554m	6.076ms	1	1	100.00
V2	chip_sw_power_idle_load	chip_sw_power_idle_load	3.462m	3.796ms	0	1	0.00
V2	chip_sw_power_sleep_load	chip_sw_power_sleep_load	3.584m	3.326ms	0	1	0.00
V2	chip_sw_exit_test_unlocked_bootstrap	chip_sw_exit_test_unlocked_bootstrap	1.861h	54.952ms	1	1	100.00
V2	chip_sw_inject_scramble_seed	chip_sw_inject_scramble_seed	1.834h	57.794ms	1	1	100.00
V2	tl_d_oob_addr_access	chip_tl_errors	1.078m	2.878ms	0	1	0.00
V2	tl_d_illegal_access	chip_tl_errors	1.078m	2.878ms	0	1	0.00
V2	tl_d_outstanding_access	chip_csr_aliasing	1.168h	35.385ms	1	1	100.00
		chip_same_csr_outstanding	45.717m	28.708ms	1	1	100.00
		chip_csr_hw_reset	3.614m	7.487ms	1	1	100.00
		chip_csr_rw	2.811m	3.818ms	1	1	100.00
V2	tl_d_partial_access	chip_csr_aliasing	1.168h	35.385ms	1	1	100.00
		chip_same_csr_outstanding	45.717m	28.708ms	1	1	100.00
		chip_csr_hw_reset	3.614m	7.487ms	1	1	100.00
		chip_csr_rw	2.811m	3.818ms	1	1	100.00
V2	xbar_base_random_sequence	xbar_random	17.670s	856.740us	1	1	100.00
V2	xbar_random_delay	xbar_smoke_zero_delays	5.130s	47.193us	1	1	100.00
		xbar_smoke_large_delays	35.210s	5.966ms	1	1	100.00
		xbar_smoke_slow_rsp	50.380s	6.100ms	1	1	100.00
		xbar_random_zero_delays	12.980s	209.375us	1	1	100.00
		xbar_random_large_delays	1.855m	18.599ms	1	1	100.00
		xbar_random_slow_rsp	3.023m	21.629ms	1	1	100.00
V2	xbar_unmapped_address	xbar_unmapped_addr	19.890s	313.671us	1	1	100.00
		xbar_error_and_unmapped_addr	27.280s	1.297ms	1	1	100.00
V2	xbar_error_cases	xbar_error_random	34.620s	1.924ms	1	1	100.00
		xbar_error_and_unmapped_addr	27.280s	1.297ms	1	1	100.00
V2	xbar_all_access_same_device	xbar_access_same_device	1.127m	3.167ms	1	1	100.00
		xbar_access_same_device_slow_rsp	9.416m	65.741ms	1	1	100.00
V2	xbar_all_hosts_use_same_source_id	xbar_same_source	24.400s	566.772us	1	1	100.00
V2	xbar_stress_all	xbar_stress_all	3.798m	10.881ms	1	1	100.00
		xbar_stress_all_with_error	1.730m	4.974ms	1	1	100.00
V2	xbar_stress_with_reset	xbar_stress_all_with_rand_reset	1.496m	450.716us	1	1	100.00
		xbar_stress_all_with_reset_error	1.090m	1.203ms	1	1	100.00
V2	rom_e2e_smoke	rom_e2e_smoke	40.168m	14.300ms	1	1	100.00
V2	rom_e2e_shutdown_output	rom_e2e_shutdown_output	33.904m	28.455ms	1	1	100.00
V2	rom_e2e_shutdown_exception_c	rom_e2e_shutdown_exception_c	38.990m	15.181ms	1	1	100.00
V2	rom_e2e_boot_policy_valid	rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0	31.233m	10.944ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_dev	38.866m	16.127ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod	39.269m	15.116ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod_end	39.633m	15.243ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_rma	40.446m	14.441ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0	29.340s	10.180us	0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_dev	33.920s	10.260us	0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod	34.820s	10.320us	0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod_end	32.100s	10.140us	0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_rma	29.660s	10.200us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0	29.680s	10.160us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_dev	30.640s	10.180us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod	28.370s	10.400us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod_end	28.050s	10.200us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_rma	27.690s	10.260us	0	1	0.00
V2	rom_e2e_sigverify_always	rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0	26.780s	10.300us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_dev	26.930s	10.360us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod	27.110s	10.400us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod_end	25.810s	10.280us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_rma	25.540s	10.320us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0	26.580s	10.380us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_dev	27.430s	10.100us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod	28.650s	10.280us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod_end	27.860s	10.260us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_rma	26.740s	10.380us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0	28.540s	10.220us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_dev	28.030s	10.340us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod	34.080s	10.260us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod_end	28.480s	10.340us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_rma	31.160s	10.340us	0	1	0.00
V2	rom_e2e_asm_init	rom_e2e_asm_init_test_unlocked0	29.914m	11.117ms	1	1	100.00
		rom_e2e_asm_init_dev	39.492m	15.295ms	1	1	100.00
		rom_e2e_asm_init_prod	36.853m	15.575ms	1	1	100.00
		rom_e2e_asm_init_prod_end	38.429m	16.064ms	1	1	100.00
		rom_e2e_asm_init_rma	37.390m	15.024ms	1	1	100.00
V2	rom_e2e_keymgr_init	rom_e2e_keymgr_init_rom_ext_meas	35.558m	15.558ms	1	1	100.00
		rom_e2e_keymgr_init_rom_ext_no_meas	37.423m	14.469ms	1	1	100.00
		rom_e2e_keymgr_init_rom_ext_invalid_meas	34.813m	15.480ms	1	1	100.00
V2	rom_e2e_static_critical	rom_e2e_static_critical	38.189m	15.533ms	1	1	100.00
V2	chip_sw_adc_ctrl_debug_cable_irq	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	47.939m	34.307ms	0	1	0.00
V2	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	47.939m	34.307ms	0	1	0.00
V2	chip_sw_aes_enc	chip_sw_aes_enc	2.569m	2.677ms	1	1	100.00
		chip_sw_aes_enc_jitter_en	2.124m	2.539ms	1	1	100.00
V2	chip_sw_aes_entropy	chip_sw_aes_entropy	2.631m	2.811ms	1	1	100.00
V2	chip_sw_aes_idle	chip_sw_aes_idle	2.916m	2.834ms	1	1	100.00
V2	chip_sw_aes_sideload	chip_sw_keymgr_sideload_aes	14.970m	7.886ms	1	1	100.00
V2	chip_sw_alert_handler_alerts	chip_sw_alert_test	2.870m	3.044ms	0	1	0.00
V2	chip_sw_alert_handler_escalations	chip_sw_alert_handler_escalation	5.094m	4.681ms	1	1	100.00
V2	chip_sw_all_escalation_resets	chip_sw_all_escalation_resets	6.553m	6.149ms	1	1	100.00
V2	chip_sw_alert_handler_irqs	chip_plic_all_irqs_0	9.339m	5.709ms	1	1	100.00
		chip_plic_all_irqs_10	3.890m	3.602ms	1	1	100.00
		chip_plic_all_irqs_20	5.710m	4.487ms	1	1	100.00
V2	chip_sw_alert_handler_entropy	chip_sw_alert_handler_entropy	2.652m	3.120ms	1	1	100.00
V2	chip_sw_alert_handler_crashdump	chip_sw_rstmgr_alert_info	17.061m	14.755ms	1	1	100.00
V2	chip_sw_alert_handler_ping_timeout	chip_sw_alert_handler_ping_timeout	3.076m	3.441ms	1	1	100.00
V2	chip_sw_alert_handler_lpg_sleep_mode_alerts	chip_sw_alert_handler_lpg_sleep_mode_alerts	2.627m	2.384ms	0	1	0.00
V2	chip_sw_alert_handler_lpg_sleep_mode_pings	chip_sw_alert_handler_lpg_sleep_mode_pings	10.651m	12.110ms	1	1	100.00
V2	chip_sw_alert_handler_lpg_clock_off	chip_sw_alert_handler_lpg_clkoff	15.706m	7.372ms	1	1	100.00
V2	chip_sw_alert_handler_lpg_reset_toggle	chip_sw_alert_handler_lpg_reset_toggle	13.184m	6.782ms	1	1	100.00
V2	chip_sw_alert_handler_ping_ok	chip_sw_alert_handler_ping_ok	11.794m	7.770ms	1	1	100.00
V2	chip_sw_alert_handler_reverse_ping_in_deep_sleep	chip_sw_alert_handler_reverse_ping_in_deep_sleep	2.236h	256.041ms	1	1	100.00
V2	chip_sw_aon_timer_wakeup_irq	chip_sw_aon_timer_irq	3.955m	4.258ms	1	1	100.00
V2	chip_sw_aon_timer_sleep_wakeup	chip_sw_pwrmgr_smoketest	5.016m	6.687ms	1	1	100.00
V2	chip_sw_aon_timer_wdog_bark_irq	chip_sw_aon_timer_irq	3.955m	4.258ms	1	1	100.00
V2	chip_sw_aon_timer_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	7.381m	7.074ms	1	1	100.00
V2	chip_sw_aon_timer_sleep_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	7.381m	7.074ms	1	1	100.00
V2	chip_sw_aon_timer_sleep_wdog_sleep_pause	chip_sw_aon_timer_sleep_wdog_sleep_pause	4.394m	7.163ms	1	1	100.00
V2	chip_sw_aon_timer_wdog_lc_escalate	chip_sw_aon_timer_wdog_lc_escalate	4.930m	5.881ms	1	1	100.00
V2	chip_sw_clkmgr_idle_trans	chip_sw_otbn_randomness	8.778m	6.422ms	1	1	100.00
		chip_sw_aes_idle	2.916m	2.834ms	1	1	100.00
		chip_sw_hmac_enc_idle	2.531m	2.800ms	1	1	100.00
		chip_sw_kmac_idle	2.099m	3.114ms	1	1	100.00
V2	chip_sw_clkmgr_off_trans	chip_sw_clkmgr_off_aes_trans	3.756m	4.546ms	1	1	100.00
		chip_sw_clkmgr_off_hmac_trans	4.916m	4.298ms	1	1	100.00
		chip_sw_clkmgr_off_kmac_trans	4.081m	5.006ms	1	1	100.00
		chip_sw_clkmgr_off_otbn_trans	3.802m	4.542ms	1	1	100.00
V2	chip_sw_clkmgr_off_peri	chip_sw_clkmgr_off_peri	12.759m	9.460ms	1	1	100.00
V2	chip_sw_clkmgr_div	chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	6.301m	4.046ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	5.925m	5.029ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	5.162m	3.997ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	5.799m	4.848ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	5.762m	4.281ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	5.489m	5.109ms	1	1	100.00
		chip_sw_ast_clk_outputs	9.093m	8.322ms	1	1	100.00
V2	chip_sw_clkmgr_external_clk_src_for_lc	chip_sw_clkmgr_external_clk_src_for_lc	5.167m	7.073ms	1	1	100.00
V2	chip_sw_clkmgr_external_clk_src_for_sw	chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	5.162m	3.997ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	5.799m	4.848ms	1	1	100.00
V2	chip_sw_clkmgr_jitter	chip_sw_flash_ctrl_ops_jitter_en	5.786m	3.918ms	1	1	100.00
		chip_sw_flash_ctrl_access_jitter_en	10.319m	6.702ms	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	52.687m	18.497ms	1	1	100.00
		chip_sw_aes_enc_jitter_en	2.124m	2.539ms	1	1	100.00
		chip_sw_edn_entropy_reqs_jitter	10.893m	6.549ms	1	1	100.00
		chip_sw_hmac_enc_jitter_en	2.779m	2.841ms	1	1	100.00
		chip_sw_keymgr_key_derivation_jitter_en	9.370m	6.450ms	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en	2.434m	2.954ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	5.152m	4.096ms	1	1	100.00
		chip_sw_clkmgr_jitter	3.111m	2.656ms	1	1	100.00
V2	chip_sw_clkmgr_extended_range	chip_sw_clkmgr_jitter_reduced_freq	1.997m	2.152ms	1	1	100.00
		chip_sw_flash_ctrl_ops_jitter_en_reduced_freq	6.408m	4.369ms	1	1	100.00
		chip_sw_flash_ctrl_access_jitter_en_reduced_freq	9.790m	7.116ms	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq	48.328m	23.596ms	1	1	100.00
		chip_sw_aes_enc_jitter_en_reduced_freq	2.515m	3.259ms	1	1	100.00
		chip_sw_hmac_enc_jitter_en_reduced_freq	2.907m	3.645ms	1	1	100.00
		chip_sw_keymgr_key_derivation_jitter_en_reduced_freq	20.693m	12.299ms	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en_reduced_freq	2.770m	3.150ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq	5.821m	5.395ms	1	1	100.00
		chip_sw_flash_init_reduced_freq	16.530m	19.109ms	1	1	100.00
		chip_sw_csrng_edn_concurrency_reduced_freq	1.002h	37.506ms	1	1	100.00
V2	chip_sw_clkmgr_deep_sleep_frequency	chip_sw_ast_clk_outputs	9.093m	8.322ms	1	1	100.00
V2	chip_sw_clkmgr_sleep_frequency	chip_sw_clkmgr_sleep_frequency	5.148m	4.772ms	1	1	100.00
V2	chip_sw_clkmgr_reset_frequency	chip_sw_clkmgr_reset_frequency	4.053m	3.366ms	1	1	100.00
V2	chip_sw_clkmgr_escalation_reset	chip_sw_all_escalation_resets	6.553m	6.149ms	1	1	100.00
V2	chip_sw_clkmgr_alert_handler_clock_enables	chip_sw_alert_handler_lpg_clkoff	15.706m	7.372ms	1	1	100.00
V2	chip_sw_csrng_edn_cmd	chip_sw_entropy_src_csrng	11.412m	5.583ms	1	1	100.00
V2	chip_sw_csrng_fuse_en_sw_app_read	chip_sw_csrng_fuse_en_sw_app_read_test	1.800m	2.154ms	0	1	0.00
V2	chip_sw_csrng_lc_hw_debug_en	chip_sw_csrng_lc_hw_debug_en_test	6.218m	6.576ms	1	1	100.00
V2	chip_sw_csrng_known_answer_tests	chip_sw_csrng_kat_test	2.158m	2.965ms	1	1	100.00
V2	chip_sw_edn_entropy_reqs	chip_sw_csrng_edn_concurrency	1.010h	23.601ms	1	1	100.00
		chip_sw_entropy_src_ast_rng_req	2.899m	3.161ms	1	1	100.00
		chip_sw_edn_entropy_reqs	10.706m	5.625ms	1	1	100.00
V2	chip_sw_entropy_src_ast_rng_req	chip_sw_entropy_src_ast_rng_req	2.899m	3.161ms	1	1	100.00
V2	chip_sw_entropy_src_csrng	chip_sw_entropy_src_csrng	11.412m	5.583ms	1	1	100.00
V2	chip_sw_entropy_src_known_answer_tests	chip_sw_entropy_src_kat_test	2.491m	2.935ms	1	1	100.00
V2	chip_sw_flash_init	chip_sw_flash_init	20.745m	16.706ms	1	1	100.00
V2	chip_sw_flash_host_access	chip_sw_flash_ctrl_access	8.969m	6.031ms	1	1	100.00
		chip_sw_flash_ctrl_access_jitter_en	10.319m	6.702ms	1	1	100.00
V2	chip_sw_flash_ctrl_ops	chip_sw_flash_ctrl_ops	5.439m	3.804ms	1	1	100.00
		chip_sw_flash_ctrl_ops_jitter_en	5.786m	3.918ms	1	1	100.00
V2	chip_sw_flash_rma_unlocked	chip_sw_flash_rma_unlocked	52.573m	42.594ms	1	1	100.00
V2	chip_sw_flash_scramble	chip_sw_flash_init	20.745m	16.706ms	1	1	100.00
V2	chip_sw_flash_idle_low_power	chip_sw_flash_ctrl_idle_low_power	3.266m	3.068ms	1	1	100.00
V2	chip_sw_flash_keymgr_seeds	chip_sw_keymgr_key_derivation	20.377m	9.188ms	1	1	100.00
V2	chip_sw_flash_lc_creator_seed_sw_rw_en	chip_sw_flash_ctrl_lc_rw_en	5.918m	6.020ms	1	1	100.00
V2	chip_sw_flash_creator_seed_wipe_on_rma	chip_sw_flash_rma_unlocked	52.573m	42.594ms	1	1	100.00
V2	chip_sw_flash_lc_owner_seed_sw_rw_en	chip_sw_flash_ctrl_lc_rw_en	5.918m	6.020ms	1	1	100.00
V2	chip_sw_flash_lc_iso_part_sw_rd_en	chip_sw_flash_ctrl_lc_rw_en	5.918m	6.020ms	1	1	100.00
V2	chip_sw_flash_lc_iso_part_sw_wr_en	chip_sw_flash_ctrl_lc_rw_en	5.918m	6.020ms	1	1	100.00
V2	chip_sw_flash_lc_seed_hw_rd_en	chip_sw_flash_ctrl_lc_rw_en	5.918m	6.020ms	1	1	100.00
V2	chip_sw_flash_lc_escalate_en	chip_sw_all_escalation_resets	6.553m	6.149ms	1	1	100.00
V2	chip_sw_flash_prim_tl_access	chip_prim_tl_access	5.683m	14.480ms	1	1	100.00
V2	chip_sw_flash_ctrl_clock_freqs	chip_sw_flash_ctrl_clock_freqs	8.246m	4.755ms	1	1	100.00
V2	chip_sw_flash_ctrl_escalation_reset	chip_sw_flash_crash_alert	7.135m	6.091ms	1	1	100.00
V2	chip_sw_flash_ctrl_write_clear	chip_sw_flash_crash_alert	7.135m	6.091ms	1	1	100.00
V2	chip_sw_hmac_enc	chip_sw_hmac_enc	2.219m	2.883ms	1	1	100.00
		chip_sw_hmac_enc_jitter_en	2.779m	2.841ms	1	1	100.00
V2	chip_sw_hmac_idle	chip_sw_hmac_enc_idle	2.531m	2.800ms	1	1	100.00
V2	chip_sw_hmac_all_configurations	chip_sw_hmac_oneshot	3.404m	2.641ms	1	1	100.00
V2	chip_sw_hmac_multistream_mode	chip_sw_hmac_multistream	14.663m	6.812ms	1	1	100.00
V2	chip_sw_i2c_host_tx_rx	chip_sw_i2c_host_tx_rx	7.183m	4.905ms	1	1	100.00
		chip_sw_i2c_host_tx_rx_idx1	5.769m	5.658ms	1	1	100.00
		chip_sw_i2c_host_tx_rx_idx2	6.909m	5.644ms	1	1	100.00
V2	chip_sw_i2c_device_tx_rx	chip_sw_i2c_device_tx_rx	4.481m	3.947ms	1	1	100.00
V2	chip_sw_keymgr_key_derivation	chip_sw_keymgr_key_derivation	20.377m	9.188ms	1	1	100.00
		chip_sw_keymgr_key_derivation_jitter_en	9.370m	6.450ms	1	1	100.00
V2	chip_sw_keymgr_sideload_kmac	chip_sw_keymgr_sideload_kmac	27.238m	12.296ms	1	1	100.00
V2	chip_sw_keymgr_sideload_aes	chip_sw_keymgr_sideload_aes	14.970m	7.886ms	1	1	100.00
V2	chip_sw_keymgr_sideload_otbn	chip_sw_keymgr_sideload_otbn	36.859m	12.872ms	1	1	100.00
V2	chip_sw_kmac_enc	chip_sw_kmac_mode_cshake	2.133m	2.553ms	1	1	100.00
		chip_sw_kmac_mode_kmac	2.806m	3.731ms	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en	2.434m	2.954ms	1	1	100.00
V2	chip_sw_kmac_app_keymgr	chip_sw_keymgr_key_derivation	20.377m	9.188ms	1	1	100.00
V2	chip_sw_kmac_app_lc	chip_sw_lc_ctrl_transition	5.782m	6.247ms	1	1	100.00
V2	chip_sw_kmac_app_rom	chip_sw_kmac_app_rom	2.775m	2.396ms	1	1	100.00
V2	chip_sw_kmac_entropy	chip_sw_kmac_entropy	22.431m	10.116ms	1	1	100.00
V2	chip_sw_kmac_idle	chip_sw_kmac_idle	2.099m	3.114ms	1	1	100.00
V2	chip_sw_lc_ctrl_alert_handler_escalation	chip_sw_alert_handler_escalation	5.094m	4.681ms	1	1	100.00
V2	chip_sw_lc_ctrl_jtag_access	chip_tap_straps_dev	6.156m	6.992ms	1	1	100.00
		chip_tap_straps_rma	2.081m	3.487ms	1	1	100.00
		chip_tap_straps_prod	18.589m	17.903ms	1	1	100.00
V2	chip_sw_lc_ctrl_otp_hw_cfg0	chip_sw_lc_ctrl_otp_hw_cfg0	2.078m	2.839ms	1	1	100.00
V2	chip_sw_lc_ctrl_init	chip_sw_lc_ctrl_transition	5.782m	6.247ms	1	1	100.00
V2	chip_sw_lc_ctrl_transitions	chip_sw_lc_ctrl_transition	5.782m	6.247ms	1	1	100.00
V2	chip_sw_lc_ctrl_kmac_req	chip_sw_lc_ctrl_transition	5.782m	6.247ms	1	1	100.00
V2	chip_sw_lc_ctrl_key_div	chip_sw_keymgr_key_derivation_prod	20.450m	10.855ms	1	1	100.00
V2	chip_sw_lc_ctrl_broadcast	chip_sw_flash_ctrl_lc_rw_en	5.918m	6.020ms	1	1	100.00
		chip_sw_flash_rma_unlocked	52.573m	42.594ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_test_unlocked0	3.445m	3.517ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_dev	7.096m	5.409ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_prod	9.983m	7.486ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_rma	8.621m	6.706ms	1	1	100.00
		chip_sw_lc_ctrl_transition	5.782m	6.247ms	1	1	100.00
		chip_sw_keymgr_key_derivation	20.377m	9.188ms	1	1	100.00
		chip_sw_rom_ctrl_integrity_check	5.189m	8.367ms	1	1	100.00
		chip_sw_sram_ctrl_execution_main	5.625m	6.391ms	1	1	100.00
		chip_prim_tl_access	5.683m	14.480ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_lc	5.167m	7.073ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	6.301m	4.046ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	5.925m	5.029ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	5.162m	3.997ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	5.799m	4.848ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	5.762m	4.281ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	5.489m	5.109ms	1	1	100.00
		chip_tap_straps_dev	6.156m	6.992ms	1	1	100.00
		chip_tap_straps_rma	2.081m	3.487ms	1	1	100.00
		chip_tap_straps_prod	18.589m	17.903ms	1	1	100.00
		chip_rv_dm_lc_disabled	6.188m	14.653ms	1	1	100.00
V2	chip_lc_scrap	chip_sw_lc_ctrl_rma_to_scrap	2.929m	3.498ms	1	1	100.00
		chip_sw_lc_ctrl_raw_to_scrap	1.749m	3.784ms	1	1	100.00
		chip_sw_lc_ctrl_test_locked0_to_scrap	1.455m	3.430ms	1	1	100.00
		chip_sw_lc_ctrl_rand_to_scrap	2.802m	3.411ms	1	1	100.00
V2	chip_lc_test_locked	chip_sw_lc_walkthrough_testunlocks	22.873m	28.879ms	1	1	100.00
		chip_rv_dm_lc_disabled	6.188m	14.653ms	1	1	100.00
V2	chip_sw_lc_walkthrough	chip_sw_lc_walkthrough_dev	1.122h	50.446ms	1	1	100.00
		chip_sw_lc_walkthrough_prod	1.000h	46.656ms	1	1	100.00
		chip_sw_lc_walkthrough_prodend	7.376m	9.070ms	1	1	100.00
		chip_sw_lc_walkthrough_rma	1.007h	47.642ms	1	1	100.00
		chip_sw_lc_walkthrough_testunlocks	22.873m	28.879ms	1	1	100.00
V2	chip_sw_lc_ctrl_volatile_raw_unlock	chip_sw_lc_ctrl_volatile_raw_unlock	1.287m	2.365ms	1	1	100.00
		chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz	1.155m	2.922ms	1	1	100.00
		rom_volatile_raw_unlock	1.483m	2.620ms	1	1	100.00
V2	chip_sw_otbn_op	chip_sw_otbn_ecdsa_op_irq	53.499m	16.702ms	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	52.687m	18.497ms	1	1	100.00
V2	chip_sw_otbn_rnd_entropy	chip_sw_otbn_randomness	8.778m	6.422ms	1	1	100.00
V2	chip_sw_otbn_urnd_entropy	chip_sw_otbn_randomness	8.778m	6.422ms	1	1	100.00
V2	chip_sw_otbn_idle	chip_sw_otbn_randomness	8.778m	6.422ms	1	1	100.00
V2	chip_sw_otbn_mem_scramble	chip_sw_otbn_mem_scramble	4.092m	3.116ms	1	1	100.00
V2	chip_otp_ctrl_init	chip_sw_lc_ctrl_transition	5.782m	6.247ms	1	1	100.00
V2	chip_sw_otp_ctrl_keys	chip_sw_flash_init	20.745m	16.706ms	1	1	100.00
		chip_sw_otbn_mem_scramble	4.092m	3.116ms	1	1	100.00
		chip_sw_keymgr_key_derivation	20.377m	9.188ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access	6.603m	4.319ms	1	1	100.00
		chip_sw_rv_core_ibex_icache_invalidate	2.484m	3.121ms	1	1	100.00
V2	chip_sw_otp_ctrl_entropy	chip_sw_flash_init	20.745m	16.706ms	1	1	100.00
		chip_sw_otbn_mem_scramble	4.092m	3.116ms	1	1	100.00
		chip_sw_keymgr_key_derivation	20.377m	9.188ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access	6.603m	4.319ms	1	1	100.00
		chip_sw_rv_core_ibex_icache_invalidate	2.484m	3.121ms	1	1	100.00
V2	chip_sw_otp_ctrl_program	chip_sw_lc_ctrl_transition	5.782m	6.247ms	1	1	100.00
V2	chip_sw_otp_ctrl_program_error	chip_sw_lc_ctrl_program_error	5.677m	5.392ms	1	1	100.00
V2	chip_sw_otp_ctrl_hw_cfg0	chip_sw_lc_ctrl_otp_hw_cfg0	2.078m	2.839ms	1	1	100.00
V2	chip_sw_otp_ctrl_lc_signals	chip_sw_otp_ctrl_lc_signals_test_unlocked0	3.445m	3.517ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_dev	7.096m	5.409ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_prod	9.983m	7.486ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_rma	8.621m	6.706ms	1	1	100.00
		chip_sw_lc_ctrl_transition	5.782m	6.247ms	1	1	100.00
		chip_prim_tl_access	5.683m	14.480ms	1	1	100.00
V2	chip_sw_otp_prim_tl_access	chip_prim_tl_access	5.683m	14.480ms	1	1	100.00
V2	chip_sw_otp_ctrl_dai_lock	chip_sw_otp_ctrl_dai_lock	17.441m	8.892ms	1	1	100.00
V2	chip_sw_pwrmgr_external_full_reset	chip_sw_pwrmgr_full_aon_reset	4.072m	8.642ms	1	1	100.00
V2	chip_sw_pwrmgr_random_sleep_all_wake_ups	chip_sw_pwrmgr_random_sleep_all_wake_ups	14.844m	26.331ms	1	1	100.00
V2	chip_sw_pwrmgr_normal_sleep_all_wake_ups	chip_sw_pwrmgr_normal_sleep_all_wake_ups	4.323m	7.714ms	1	1	100.00
V2	chip_sw_pwrmgr_deep_sleep_por_reset	chip_sw_pwrmgr_deep_sleep_por_reset	5.099m	6.856ms	1	1	100.00
V2	chip_sw_pwrmgr_normal_sleep_por_reset	chip_sw_pwrmgr_normal_sleep_por_reset	5.763m	5.676ms	1	1	100.00
V2	chip_sw_pwrmgr_deep_sleep_all_wake_ups	chip_sw_pwrmgr_deep_sleep_all_wake_ups	12.458m	20.023ms	1	1	100.00
V2	chip_sw_pwrmgr_deep_sleep_all_reset_reqs	chip_sw_pwrmgr_deep_sleep_all_reset_reqs	13.794m	16.954ms	1	1	100.00
		chip_sw_aon_timer_wdog_bite_reset	7.381m	7.074ms	1	1	100.00
V2	chip_sw_pwrmgr_normal_sleep_all_reset_reqs	chip_sw_pwrmgr_normal_sleep_all_reset_reqs	11.876m	10.401ms	1	1	100.00
V2	chip_sw_pwrmgr_wdog_reset	chip_sw_pwrmgr_wdog_reset	4.466m	4.480ms	1	1	100.00
V2	chip_sw_pwrmgr_aon_power_glitch_reset	chip_sw_pwrmgr_full_aon_reset	4.072m	8.642ms	1	1	100.00
V2	chip_sw_pwrmgr_main_power_glitch_reset	chip_sw_pwrmgr_main_power_glitch_reset	4.714m	4.621ms	1	1	100.00
V2	chip_sw_pwrmgr_random_sleep_power_glitch_reset	chip_sw_pwrmgr_random_sleep_power_glitch_reset	30.347m	29.560ms	1	1	100.00
V2	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	3.692m	6.821ms	1	1	100.00
V2	chip_sw_pwrmgr_sleep_power_glitch_reset	chip_sw_pwrmgr_sleep_power_glitch_reset	3.510m	4.422ms	1	1	100.00
V2	chip_sw_pwrmgr_random_sleep_all_reset_reqs	chip_sw_pwrmgr_random_sleep_all_reset_reqs	21.705m	21.141ms	1	1	100.00
V2	chip_sw_pwrmgr_sysrst_ctrl_reset	chip_sw_pwrmgr_sysrst_ctrl_reset	11.265m	8.861ms	1	1	100.00
		chip_sw_pwrmgr_all_reset_reqs	11.691m	12.339ms	1	1	100.00
V2	chip_sw_pwrmgr_b2b_sleep_reset_req	chip_sw_pwrmgr_b2b_sleep_reset_req	20.334m	22.939ms	1	1	100.00
V2	chip_sw_pwrmgr_sleep_disabled	chip_sw_pwrmgr_sleep_disabled	3.266m	3.412ms	1	1	100.00
V2	chip_sw_pwrmgr_escalation_reset	chip_sw_all_escalation_resets	6.553m	6.149ms	1	1	100.00
V2	chip_sw_rom_access	chip_sw_rom_ctrl_integrity_check	5.189m	8.367ms	1	1	100.00
V2	chip_sw_rom_ctrl_integrity_check	chip_sw_rom_ctrl_integrity_check	5.189m	8.367ms	1	1	100.00
V2	chip_sw_rstmgr_non_sys_reset_info	chip_sw_pwrmgr_all_reset_reqs	11.691m	12.339ms	1	1	100.00
		chip_sw_pwrmgr_random_sleep_all_reset_reqs	21.705m	21.141ms	1	1	100.00
		chip_sw_pwrmgr_wdog_reset	4.466m	4.480ms	1	1	100.00
		chip_sw_pwrmgr_smoketest	5.016m	6.687ms	1	1	100.00
V2	chip_sw_rstmgr_sys_reset_info	chip_rv_dm_ndm_reset_req	3.320m	4.439ms	1	1	100.00
V2	chip_sw_rstmgr_cpu_info	chip_sw_rstmgr_cpu_info	3.255m	3.746ms	0	1	0.00
V2	chip_sw_rstmgr_sw_req_reset	chip_sw_rstmgr_sw_req	3.790m	4.408ms	1	1	100.00
V2	chip_sw_rstmgr_alert_info	chip_sw_rstmgr_alert_info	17.061m	14.755ms	1	1	100.00
V2	chip_sw_rstmgr_sw_rst	chip_sw_rstmgr_sw_rst	2.179m	2.668ms	1	1	100.00
V2	chip_sw_rstmgr_escalation_reset	chip_sw_all_escalation_resets	6.553m	6.149ms	1	1	100.00
V2	chip_sw_rstmgr_alert_handler_reset_enables	chip_sw_alert_handler_lpg_reset_toggle	13.184m	6.782ms	1	1	100.00
V2	chip_sw_nmi_irq	chip_sw_rv_core_ibex_nmi_irq	7.485m	4.832ms	1	1	100.00
V2	chip_sw_rv_core_ibex_rnd	chip_sw_rv_core_ibex_rnd	7.666m	4.958ms	1	1	100.00
V2	chip_sw_rv_core_ibex_address_translation	chip_sw_rv_core_ibex_address_translation	2.302m	2.566ms	1	1	100.00
V2	chip_sw_rv_core_ibex_icache_scrambled_access	chip_sw_rv_core_ibex_icache_invalidate	2.484m	3.121ms	1	1	100.00
V2	chip_sw_rv_core_ibex_fault_dump	chip_sw_rstmgr_cpu_info	3.255m	3.746ms	0	1	0.00
V2	chip_sw_rv_core_ibex_double_fault	chip_sw_rstmgr_cpu_info	3.255m	3.746ms	0	1	0.00
V2	chip_jtag_csr_rw	chip_jtag_csr_rw	29.476m	20.239ms	1	1	100.00
V2	chip_jtag_mem_access	chip_jtag_mem_access	15.311m	13.890ms	1	1	100.00
V2	chip_rv_dm_ndm_reset_req	chip_rv_dm_ndm_reset_req	3.320m	4.439ms	1	1	100.00
V2	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	3.300m	3.972ms	1	1	100.00
V2	chip_rv_dm_access_after_wakeup	chip_sw_rv_dm_access_after_wakeup	3.507m	4.861ms	1	1	100.00
V2	chip_sw_rv_dm_jtag_tap_sel	chip_tap_straps_rma	2.081m	3.487ms	1	1	100.00
V2	chip_rv_dm_lc_disabled	chip_rv_dm_lc_disabled	6.188m	14.653ms	1	1	100.00
V2	chip_sw_plic_all_irqs	chip_plic_all_irqs_0	9.339m	5.709ms	1	1	100.00
		chip_plic_all_irqs_10	3.890m	3.602ms	1	1	100.00
		chip_plic_all_irqs_20	5.710m	4.487ms	1	1	100.00
V2	chip_sw_plic_sw_irq	chip_sw_plic_sw_irq	2.286m	2.850ms	1	1	100.00
V2	chip_sw_timer	chip_sw_rv_timer_irq	2.740m	2.719ms	1	1	100.00
V2	chip_sw_spi_device_flash_mode	rom_e2e_smoke	40.168m	14.300ms	1	1	100.00
V2	chip_sw_spi_device_pass_through	chip_sw_spi_device_pass_through	6.222m	6.223ms	1	1	100.00
V2	chip_sw_spi_device_pass_through_collision	chip_sw_spi_device_pass_through_collision	3.397m	3.764ms	0	1	0.00
V2	chip_sw_spi_device_tpm	chip_sw_spi_device_tpm	2.969m	3.111ms	1	1	100.00
V2	chip_sw_spi_host_tx_rx	chip_sw_spi_host_tx_rx	2.891m	3.332ms	1	1	100.00
V2	chip_sw_sram_scrambled_access	chip_sw_sram_ctrl_scrambled_access	6.603m	4.319ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	5.152m	4.096ms	1	1	100.00
V2	chip_sw_sleep_sram_ret_contents	chip_sw_sleep_sram_ret_contents_no_scramble	5.514m	6.406ms	1	1	100.00
		chip_sw_sleep_sram_ret_contents_scramble	7.781m	7.541ms	1	1	100.00
V2	chip_sw_sram_execution	chip_sw_sram_ctrl_execution_main	5.625m	6.391ms	1	1	100.00
V2	chip_sw_sram_lc_escalation	chip_sw_all_escalation_resets	6.553m	6.149ms	1	1	100.00
		chip_sw_data_integrity_escalation	6.174m	5.718ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_reset	chip_sw_pwrmgr_sysrst_ctrl_reset	11.265m	8.861ms	1	1	100.00
		chip_sw_sysrst_ctrl_reset	16.903m	22.145ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_inputs	chip_sw_sysrst_ctrl_inputs	2.023m	3.100ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_outputs	chip_sw_sysrst_ctrl_outputs	3.455m	3.752ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_in_irq	chip_sw_sysrst_ctrl_in_irq	4.905m	4.558ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_sleep_wakeup	chip_sw_sysrst_ctrl_reset	16.903m	22.145ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_sleep_reset	chip_sw_sysrst_ctrl_reset	16.903m	22.145ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_ec_rst_l	chip_sw_sysrst_ctrl_ec_rst_l	40.555m	20.831ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_flash_wp_l	chip_sw_sysrst_ctrl_ec_rst_l	40.555m	20.831ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_ulp_z3_wakeup	chip_sw_sysrst_ctrl_ulp_z3_wakeup	4.749m	6.470ms	1	1	100.00
		chip_sw_adc_ctrl_sleep_debug_cable_wakeup	47.939m	34.307ms	0	1	0.00
V2	chip_sw_usbdev_vbus	chip_sw_usbdev_vbus	2.348m	2.682ms	1	1	100.00
V2	chip_sw_usbdev_pullup	chip_sw_usbdev_pullup	2.299m	2.861ms	1	1	100.00
V2	chip_sw_usbdev_aon_pullup	chip_sw_usbdev_aon_pullup	4.099m	3.717ms	1	1	100.00
V2	chip_sw_usbdev_setup_rx	chip_sw_usbdev_setuprx	5.374m	3.836ms	1	1	100.00
V2	chip_sw_usbdev_config_host	chip_sw_usbdev_config_host	15.925m	8.038ms	1	1	100.00
V2	chip_sw_usbdev_pincfg	chip_sw_usbdev_pincfg	1.364h	31.612ms	1	1	100.00
V2	chip_sw_usbdev_tx_rx	chip_sw_usbdev_dpi	28.203m	11.902ms	1	1	100.00
V2	chip_sw_usbdev_toggle_restore	chip_sw_usbdev_toggle_restore	2.881m	2.514ms	1	1	100.00
V2		TOTAL			239	275	86.91
V2S	chip_sw_aes_masking_off	chip_sw_aes_masking_off	2.498m	3.183ms	1	1	100.00
V2S	chip_sw_rv_core_ibex_lockstep_glitch	chip_sw_rv_core_ibex_lockstep_glitch	2.065m	2.644ms	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	chip_sw_coremark	chip_sw_coremark	2.452h	70.938ms	1	1	100.00
V3	chip_sw_power_max_load	chip_sw_power_virus	14.305m	5.815ms	1	1	100.00
V3	rom_e2e_debug	rom_e2e_jtag_debug_test_unlocked0	18.166m	10.741ms	1	1	100.00
		rom_e2e_jtag_debug_dev	16.566m	11.151ms	1	1	100.00
		rom_e2e_jtag_debug_rma	17.203m	10.798ms	1	1	100.00
V3	rom_e2e_jtag_inject	rom_e2e_jtag_inject_test_unlocked0	3.318m	4.043ms	1	1	100.00
		rom_e2e_jtag_inject_dev	2.911m	4.821ms	1	1	100.00
		rom_e2e_jtag_inject_rma	3.120m	3.261ms	1	1	100.00
V3	rom_e2e_self_hash	rom_e2e_self_hash	14.472s		0	1	0.00
V3	chip_sw_clkmgr_jitter_cycle_measurements	chip_sw_clkmgr_jitter_frequency	8.015m	5.796ms	1	1	100.00
V3	chip_sw_edn_boot_mode	chip_sw_edn_boot_mode	4.890m	3.156ms	1	1	100.00
V3	chip_sw_edn_auto_mode	chip_sw_edn_auto_mode	20.880m	8.556ms	1	1	100.00
V3	chip_sw_edn_sw_mode	chip_sw_edn_sw_mode	12.476m	6.594ms	1	1	100.00
V3	chip_sw_edn_kat	chip_sw_edn_kat	3.406m	2.777ms	1	1	100.00
V3	chip_sw_flash_memory_protection	chip_sw_flash_ctrl_mem_protection	8.398m	5.342ms	1	1	100.00
V3	chip_sw_otp_ctrl_vendor_test_csr_access	chip_sw_otp_ctrl_vendor_test_csr_access	2.292m	2.435ms	1	1	100.00
V3	chip_sw_otp_ctrl_escalation	chip_sw_otp_ctrl_escalation	6.556m	5.330ms	1	1	100.00
V3	chip_sw_sensor_ctrl_deep_sleep_wake_up	chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up	4.128m	5.017ms	1	1	100.00
V3	chip_sw_pwrmgr_usb_clk_disabled_when_active	chip_sw_pwrmgr_usb_clk_disabled_when_active	4.714m	5.316ms	1	1	100.00
V3	chip_sw_all_resets	chip_sw_pwrmgr_all_reset_reqs	11.691m	12.339ms	1	1	100.00
V3	chip_rv_dm_perform_debug	rom_e2e_jtag_debug_test_unlocked0	18.166m	10.741ms	1	1	100.00
		rom_e2e_jtag_debug_dev	16.566m	11.151ms	1	1	100.00
		rom_e2e_jtag_debug_rma	17.203m	10.798ms	1	1	100.00
V3	chip_sw_rv_dm_access_after_hw_reset	chip_sw_rv_dm_access_after_escalation_reset	4.769m	4.577ms	1	1	100.00
V3	chip_sw_plic_alerts	chip_sw_all_escalation_resets	6.553m	6.149ms	1	1	100.00
V3	tick_configuration	chip_sw_rv_timer_systick_test	1.375h	38.058ms	1	1	100.00
V3	counter_wrap	chip_sw_rv_timer_systick_test	1.375h	38.058ms	1	1	100.00
V3	chip_sw_spi_device_output_when_disabled_or_sleeping	chip_sw_spi_device_pinmux_sleep_retention	2.418m	3.773ms	1	1	100.00
V3	chip_sw_uart_watermarks	chip_sw_uart_tx_rx	5.328m	4.751ms	1	1	100.00
V3	chip_sw_usbdev_stream	chip_sw_usbdev_stream	48.663m	18.647ms	1	1	100.00
V3		TOTAL			22	23	95.65
	Unmapped tests	chip_sival_flash_info_access	2.364m	3.099ms	1	1	100.00
		chip_sw_rstmgr_rst_cnsty_escalation	5.016m	5.197ms	1	1	100.00
		chip_sw_otp_ctrl_ecc_error_vendor_test	2.239m	3.134ms	1	1	100.00
		chip_sw_otp_ctrl_descrambling	2.562m	3.371ms	1	1	100.00
		chip_sw_pwrmgr_lowpower_cancel	2.450m	2.989ms	0	1	0.00
		chip_sw_pwrmgr_sleep_wake_5_bug	10.039s		0	1	0.00
		chip_sw_flash_ctrl_write_clear	3.253m	3.126ms	1	1	100.00
		TOTAL			285	325	87.69

Failure Buckets

UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode has 11 failures:
- Test rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0 has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0.7077626965813069262412219251011336041925118783299985836176377381717836710383
    Line 605, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.160001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.160001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_bad_b_good_dev has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_bad_b_good_dev.106796631180576393351528296895898019181793985352059697580845226952820256666932
    Line 656, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_dev/latest/run.log
```
  UVM_FATAL @  10.180001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.180001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_bad_b_good_prod has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_bad_b_good_prod.35425921404089584672804251373374800822764315337775791052430382649122854498012
    Line 658, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod/latest/run.log
```
  UVM_FATAL @  10.400001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.400001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_bad_b_good_prod_end has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_bad_b_good_prod_end.105025410899230194614775001591201790832651646066435785998373592400531352773559
    Line 644, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod_end/latest/run.log
```
  UVM_FATAL @  10.200001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.200001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_bad_b_good_rma has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_bad_b_good_rma.26676516013184966410001436131796060410311264032984855444736547106467233470543
    Line 669, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_rma/latest/run.log
```
  UVM_FATAL @  10.260001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.260001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- ... and 6 more tests.
UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode has 5 failures:
- Test rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0 has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0.17992339127428841203643080178862187310988278716449066054904635201261097302589
    Line 598, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.180001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.180001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_good_b_bad_dev has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_good_b_bad_dev.51887447297063847943849200307056565802165127955042978205154569444679894400191
    Line 597, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_dev/latest/run.log
```
  UVM_FATAL @  10.260001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.260001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_good_b_bad_prod has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_good_b_bad_prod.22991974348560124337247893507312275052553187157877309330176906062837159094005
    Line 603, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod/latest/run.log
```
  UVM_FATAL @  10.320001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.320001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_good_b_bad_prod_end has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_good_b_bad_prod_end.22759689877974355473964913601729697195310606287265493044133054013076495587233
    Line 587, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod_end/latest/run.log
```
  UVM_FATAL @  10.140001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.140001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_good_b_bad_rma has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_good_b_bad_rma.75918427021736359972071157724030640712399525425082380380520296904782084298851
    Line 586, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_rma/latest/run.log
```
  UVM_FATAL @  10.200001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.200001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode has 3 failures:
- Test rom_e2e_sigverify_always_a_nothing_b_bad_prod has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_prod.14300339860475734534671837389544061445170168830944036044343345432975093902272
    Line 667, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod/latest/run.log
```
  UVM_FATAL @  10.260001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.260001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_sigverify_always_a_nothing_b_bad_prod_end has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_prod_end.16340227467451920264357621642777706415119034189543280173391542273244398434994
    Line 646, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod_end/latest/run.log
```
  UVM_FATAL @  10.340001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_sigverify_always_a_nothing_b_bad_rma has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_rma.115158562254315621108893507473229017240360875911661898413374182625132098374746
    Line 662, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_rma/latest/run.log
```
  UVM_FATAL @  10.340001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

Job returned non-zero exit code has 2 failures:

Test chip_sw_pwrmgr_sleep_wake_5_bug has 1 failures.

0.chip_sw_pwrmgr_sleep_wake_5_bug.113562684350506442236910891533752383179053627923580246924225098449585228712930
Log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_sleep_wake_5_bug/latest/run.log

  Computing main repo mapping:
  Loading:
  Loading: 0 packages loaded
  WARNING: Target pattern parsing failed.
  ERROR: Skipping '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/runs/opentitan/sw/device/tests/BUILD
  ERROR: no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/runs/opentitan/sw/device/tests/BUILD
  INFO: Elapsed time: 0.156s
  INFO: 0 processes.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test rom_e2e_self_hash has 1 failures.

0.rom_e2e_self_hash.102514824686086165856689147228107597571693321147241998812856248415769444380052
Log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_self_hash/latest/run.log

  Computing main repo mapping:
  Loading:
  Loading: 0 packages loaded
  WARNING: Target pattern parsing failed.
  ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/runs/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD
  ERROR: no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/runs/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD
  INFO: Elapsed time: 0.151s
  INFO: 0 processes.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_test_key_*.signed.*.scr.vmem could not be opened for r mode has 2 failures:
- Test rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0 has 1 failures.
  - 0.rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0.62806950826012892037312995605633884515465297387479573045826625000011146582402
    Line 801, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.300001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_test_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.300001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0 has 1 failures.
  - 0.rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0.90944181707839807963615372986045814767138340445776549421193232061318233930598
    Line 571, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.380001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_test_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.380001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_dev_key_*.signed.*.scr.vmem could not be opened for r mode has 2 failures:
- Test rom_e2e_sigverify_always_a_bad_b_bad_dev has 1 failures.
  - 0.rom_e2e_sigverify_always_a_bad_b_bad_dev.79412824922371573519295371561335421065459984756101888401138555439187815436051
    Line 798, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_bad_dev/latest/run.log
```
  UVM_FATAL @  10.360001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_dev_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.360001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_sigverify_always_a_bad_b_nothing_dev has 1 failures.
  - 0.rom_e2e_sigverify_always_a_bad_b_nothing_dev.71318916019173117409610210522963845280669995369820396028389351155925859854865
    Line 717, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_nothing_dev/latest/run.log
```
  UVM_FATAL @  10.100001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_dev_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.100001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (chip_sw_sleep_pin_mio_dio_val_vseq.sv:92) [chip_sw_sleep_pin_mio_dio_val_vseq] Check failed cfg.chip_vif.mios_if.pins[i] === exp (* [*] vs *xz [z]) for MIO[*] has 1 failures:
- Test chip_sw_sleep_pin_mio_dio_val has 1 failures.
  - 0.chip_sw_sleep_pin_mio_dio_val.107338982464665438408350039158954593567568852430503694361922757839884607131266
    Line 586, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_sleep_pin_mio_dio_val/latest/run.log
```
  UVM_ERROR @ 3000.249000 us: (chip_sw_sleep_pin_mio_dio_val_vseq.sv:92) [uvm_test_top.env.virtual_sequencer.chip_sw_sleep_pin_mio_dio_val_vseq] Check failed cfg.chip_vif.mios_if.pins[i] === exp (0x0 [0] vs 0xz [z]) for MIO[30]
  UVM_INFO @ 3000.249000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:379)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty has 1 failures:
- Test chip_sw_spi_device_pass_through_collision has 1 failures.
  - 0.chip_sw_spi_device_pass_through_collision.74058177119989897416468458156395742769573014670739121178037999257153640454613
    Line 430, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_spi_device_pass_through_collision/latest/run.log
```
  UVM_ERROR @ 3764.285048 us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:379)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty
  UVM_INFO @ 3764.285048 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR @ * us: (cip_base_scoreboard.sv:545) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@84565) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_sw_rstmgr_cpu_info has 1 failures.

0.chip_sw_rstmgr_cpu_info.50664225225401873335809198391243707053673853725969722627301347915870267571913
Line 446, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_rstmgr_cpu_info/latest/run.log

  UVM_ERROR @ 3746.118784 us: (cip_base_scoreboard.sv:545) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@84565) { a_addr: 'h8  a_data: 'h0  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h1  a_opcode: 'h0  a_user: 'h259aa  d_param: 'h0  d_source: 'h1  d_data: 'h0  d_size: 'h2  d_opcode: 'h0  d_error: 'h1  d_sink: 'h0  d_user: 'h1f2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 3746.118784 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (chip_sw_base_vseq.sv:317) virtual_sequencer [chip_sw_adc_ctrl_sleep_debug_cable_wakeup_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = * ns has 1 failures:
- Test chip_sw_adc_ctrl_sleep_debug_cable_wakeup has 1 failures.
  - 0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.51698466495856103047509083842275000014362923039180536045856211781793634897716
    Line 428, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup/latest/run.log
```
  UVM_ERROR @ 34307.146277 us: (chip_sw_base_vseq.sv:317) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_adc_ctrl_sleep_debug_cable_wakeup_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 18000000 ns

  UVM_INFO @ 34307.146277 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_test_sim_dv(hw/top_earlgrey/sw/autogen/tests/alert_test.c:322)] CHECK-fail: Expect alert *! has 1 failures:
- Test chip_sw_alert_test has 1 failures.
  - 0.chip_sw_alert_test.82686353287184748913229248607602539541123617021357378174623649822971732751415
    Line 405, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_alert_test/latest/run.log
```
  UVM_ERROR @ 3044.107640 us: (sw_logger_if.sv:526) [alert_test_sim_dv(hw/top_earlgrey/sw/autogen/tests/alert_test.c:322)] CHECK-fail: Expect alert 31!
  UVM_INFO @ 3044.107640 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0) has 1 failures:
- Test chip_sw_alert_handler_lpg_sleep_mode_alerts has 1 failures.
  - 0.chip_sw_alert_handler_lpg_sleep_mode_alerts.98775664691358118798515237515047552733513115969552987815127247050675930382276
    Line 412, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log
```
  UVM_ERROR @ 2384.481308 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
  UVM_INFO @ 2384.481308 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (cip_base_vseq.sv:587) [chip_sw_entropy_src_fuse_vseq] Check failed * == local_alert_agent_cfg.vif.get_alert() (* [*] vs * [*]) Alert usbdev_fatal_fault fired unexpectedly! has 1 failures:
- Test chip_sw_csrng_fuse_en_sw_app_read_test has 1 failures.
  - 0.chip_sw_csrng_fuse_en_sw_app_read_test.76956067892194459404108502465902921150776710054490064676567024571608748129639
    Line 408, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_csrng_fuse_en_sw_app_read_test/latest/run.log
```
  UVM_ERROR @ 2153.531019 us: (cip_base_vseq.sv:587) [uvm_test_top.env.virtual_sequencer.chip_sw_entropy_src_fuse_vseq] Check failed 0 == local_alert_agent_cfg.vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert usbdev_fatal_fault fired unexpectedly!
  UVM_INFO @ 2153.531019 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR @ * us: (cip_base_scoreboard.sv:545) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@32177) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_tl_errors has 1 failures.

0.chip_tl_errors.56141229334418457053182454035839098994767474993772061955310394200099587451153
Line 219, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_tl_errors/latest/run.log

  UVM_ERROR @ 2877.624110 us: (cip_base_scoreboard.sv:545) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@32177) { a_addr: 'h105e8  a_data: 'h2d411449  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'hd  a_opcode: 'h4  a_user: 'h1869d  d_param: 'h0  d_source: 'hd  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 2877.624110 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (sw_logger_if.sv:526) [pwrmgr_lowpower_cancel_test_sim_dv(sw/device/tests/pwrmgr_lowpower_cancel_test.c:78)] CHECK-fail: Timed out after * usec (* CPU cycles) waiting for !get_wakeup_status() has 1 failures:
- Test chip_sw_pwrmgr_lowpower_cancel has 1 failures.
  - 0.chip_sw_pwrmgr_lowpower_cancel.114996225497188762078546807015146280568815613201051762132717906148083055064405
    Line 415, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_lowpower_cancel/latest/run.log
```
  UVM_ERROR @ 2989.174378 us: (sw_logger_if.sv:526) [pwrmgr_lowpower_cancel_test_sim_dv(sw/device/tests/pwrmgr_lowpower_cancel_test.c:78)] CHECK-fail: Timed out after 100 usec (10000 CPU cycles) waiting for !get_wakeup_status()
  UVM_INFO @ 2989.174378 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (chip_sw_power_idle_load_vseq.sv:91) virtual_sequencer [chip_sw_power_idle_load_vseq] PWMCH* : pkt* Clock period is wrong. rcv : * exp : * has 1 failures:
- Test chip_sw_power_idle_load has 1 failures.
  - 0.chip_sw_power_idle_load.8846661834354429685881392270676446334404451143541003944724226078952936492521
    Line 419, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_power_idle_load/latest/run.log
```
  UVM_ERROR @ 3795.526000 us: (chip_sw_power_idle_load_vseq.sv:91) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_power_idle_load_vseq] PWMCH5 : pkt3 Clock period is wrong.  rcv : 2  exp : 32
  UVM_INFO @ 3795.526000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (chip_sw_power_sleep_load_vseq.sv:114) virtual_sequencer [chip_sw_power_sleep_load_vseq] PWMCH* : pkt* Clock period is wrong. rcv : * exp : * has 1 failures:
- Test chip_sw_power_sleep_load has 1 failures.
  - 0.chip_sw_power_sleep_load.2607442417050374544961643913177311530095833974464191675778871695395146945446
    Line 425, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_power_sleep_load/latest/run.log
```
  UVM_ERROR @ 3326.386000 us: (chip_sw_power_sleep_load_vseq.sv:114) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_power_sleep_load_vseq] PWMCH5 : pkt3 Clock period is wrong.  rcv : 2  exp : 32
  UVM_INFO @ 3326.386000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [ast_clk_rst_inputs_sim_dv(sw/device/tests/sim_dv/ast_clk_rst_inputs.c:147)] CHECK-fail: Recov alert not correctly observed in alert handler has 1 failures:
- Test chip_sw_ast_clk_rst_inputs has 1 failures.
  - 0.chip_sw_ast_clk_rst_inputs.106589905926900922222457416005810186005621189928130644049370527504306968347298
    Line 436, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_ast_clk_rst_inputs/latest/run.log
```
  UVM_ERROR @ 14131.360270 us: (sw_logger_if.sv:526) [ast_clk_rst_inputs_sim_dv(sw/device/tests/sim_dv/ast_clk_rst_inputs.c:147)] CHECK-fail: Recov alert not correctly observed in alert handler
  UVM_INFO @ 14131.360270 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_test_key_*.signed.*.scr.vmem could not be opened for r mode has 1 failures:
- Test rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0 has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0.72910771160149518229790121846753838707255701713444534830360904596826578670104
    Line 721, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.220001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_test_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.220001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_dev_key_*.signed.*.scr.vmem could not be opened for r mode has 1 failures:
- Test rom_e2e_sigverify_always_a_nothing_b_bad_dev has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_dev.37035004148893359779708165571770012691342956365546141512642687334584961164963
    Line 689, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_dev/latest/run.log
```
  UVM_FATAL @  10.340001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_dev_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR @ * us: (cip_base_scoreboard.sv:545) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@32621) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_csr_mem_rw_with_rand_reset has 1 failures.

0.chip_csr_mem_rw_with_rand_reset.101893830358304183243381616968474082338550239959758510920139018358457217368107
Line 226, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_csr_mem_rw_with_rand_reset/latest/run.log

  UVM_ERROR @ 2171.028722 us: (cip_base_scoreboard.sv:545) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@32621) { a_addr: 'h106bc  a_data: 'h9b2b06d2  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h25  a_opcode: 'h4  a_user: 'h18a09  d_param: 'h0  d_source: 'h25  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 2171.028722 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---