ADC_CTRL Simulation Results

Monday May 12 2025 18:42:29 UTC

GitHub Revision: 4f742bf

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	adc_ctrl_smoke	4.010s	5.718ms	1	1	100.00
V1	csr_hw_reset	adc_ctrl_csr_hw_reset	2.070s	680.414us	1	1	100.00
V1	csr_rw	adc_ctrl_csr_rw	1.840s	566.415us	1	1	100.00
V1	csr_bit_bash	adc_ctrl_csr_bit_bash	13.220s	26.574ms	1	1	100.00
V1	csr_aliasing	adc_ctrl_csr_aliasing	3.040s	747.275us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	adc_ctrl_csr_mem_rw_with_rand_reset	2.490s	483.281us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	adc_ctrl_csr_rw	1.840s	566.415us	1	1	100.00
		adc_ctrl_csr_aliasing	3.040s	747.275us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	filters_polled	adc_ctrl_filters_polled	3.827m	328.868ms	1	1	100.00
V2	filters_polled_fixed	adc_ctrl_filters_polled_fixed	9.934m	325.463ms	1	1	100.00
V2	filters_interrupt	adc_ctrl_filters_interrupt	1.371m	165.439ms	1	1	100.00
V2	filters_interrupt_fixed	adc_ctrl_filters_interrupt_fixed	4.399m	325.144ms	1	1	100.00
V2	filters_wakeup	adc_ctrl_filters_wakeup	5.347m	195.253ms	1	1	100.00
V2	filters_wakeup_fixed	adc_ctrl_filters_wakeup_fixed	2.814m	195.943ms	1	1	100.00
V2	filters_both	adc_ctrl_filters_both	5.048m	182.555ms	1	1	100.00
V2	clock_gating	adc_ctrl_clock_gating	4.445m	319.740ms	1	1	100.00
V2	poweron_counter	adc_ctrl_poweron_counter	3.860s	4.625ms	1	1	100.00
V2	lowpower_counter	adc_ctrl_lowpower_counter	1.253m	43.473ms	1	1	100.00
V2	fsm_reset	adc_ctrl_fsm_reset	3.218m	115.187ms	1	1	100.00
V2	stress_all	adc_ctrl_stress_all	15.430s	7.745ms	1	1	100.00
V2	alert_test	adc_ctrl_alert_test	2.810s	371.173us	1	1	100.00
V2	intr_test	adc_ctrl_intr_test	1.820s	458.141us	1	1	100.00
V2	tl_d_oob_addr_access	adc_ctrl_tl_errors	2.630s	555.650us	1	1	100.00
V2	tl_d_illegal_access	adc_ctrl_tl_errors	2.630s	555.650us	1	1	100.00
V2	tl_d_outstanding_access	adc_ctrl_csr_hw_reset	2.070s	680.414us	1	1	100.00
		adc_ctrl_csr_rw	1.840s	566.415us	1	1	100.00
		adc_ctrl_csr_aliasing	3.040s	747.275us	1	1	100.00
		adc_ctrl_same_csr_outstanding	7.990s	1.977ms	1	1	100.00
V2	tl_d_partial_access	adc_ctrl_csr_hw_reset	2.070s	680.414us	1	1	100.00
		adc_ctrl_csr_rw	1.840s	566.415us	1	1	100.00
		adc_ctrl_csr_aliasing	3.040s	747.275us	1	1	100.00
		adc_ctrl_same_csr_outstanding	7.990s	1.977ms	1	1	100.00
V2		TOTAL			16	16	100.00
V2S	tl_intg_err	adc_ctrl_sec_cm	5.410s	3.930ms	1	1	100.00
		adc_ctrl_tl_intg_err	3.380s	4.405ms	1	1	100.00
V2S	sec_cm_bus_integrity	adc_ctrl_tl_intg_err	3.380s	4.405ms	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	stress_all_with_rand_reset	adc_ctrl_stress_all_with_rand_reset	4.400s	556.509us	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			25	25	100.00