| V1 |
smoke |
aon_timer_smoke |
2.710s |
551.291us |
1 |
1 |
100.00 |
| V1 |
csr_hw_reset |
aon_timer_csr_hw_reset |
2.320s |
1.225ms |
1 |
1 |
100.00 |
| V1 |
csr_rw |
aon_timer_csr_rw |
1.620s |
424.565us |
1 |
1 |
100.00 |
| V1 |
csr_bit_bash |
aon_timer_csr_bit_bash |
3.060s |
3.503ms |
1 |
1 |
100.00 |
| V1 |
csr_aliasing |
aon_timer_csr_aliasing |
2.810s |
511.244us |
1 |
1 |
100.00 |
| V1 |
csr_mem_rw_with_rand_reset |
aon_timer_csr_mem_rw_with_rand_reset |
1.700s |
476.730us |
1 |
1 |
100.00 |
| V1 |
regwen_csr_and_corresponding_lockable_csr |
aon_timer_csr_rw |
1.620s |
424.565us |
1 |
1 |
100.00 |
|
|
aon_timer_csr_aliasing |
2.810s |
511.244us |
1 |
1 |
100.00 |
| V1 |
mem_walk |
aon_timer_mem_walk |
1.820s |
356.410us |
1 |
1 |
100.00 |
| V1 |
mem_partial_access |
aon_timer_mem_partial_access |
2.170s |
513.231us |
1 |
1 |
100.00 |
| V1 |
|
TOTAL |
|
|
8 |
8 |
100.00 |
| V2 |
prescaler |
aon_timer_prescaler |
2.280s |
509.091us |
1 |
1 |
100.00 |
| V2 |
jump |
aon_timer_jump |
2.610s |
571.522us |
1 |
1 |
100.00 |
| V2 |
stress_all |
aon_timer_stress_all |
5.655m |
284.791ms |
1 |
1 |
100.00 |
| V2 |
alert_test |
aon_timer_alert_test |
2.010s |
444.962us |
1 |
1 |
100.00 |
| V2 |
intr_test |
aon_timer_intr_test |
2.500s |
472.697us |
1 |
1 |
100.00 |
| V2 |
tl_d_oob_addr_access |
aon_timer_tl_errors |
2.410s |
493.848us |
1 |
1 |
100.00 |
| V2 |
tl_d_illegal_access |
aon_timer_tl_errors |
2.410s |
493.848us |
1 |
1 |
100.00 |
| V2 |
tl_d_outstanding_access |
aon_timer_csr_hw_reset |
2.320s |
1.225ms |
1 |
1 |
100.00 |
|
|
aon_timer_csr_rw |
1.620s |
424.565us |
1 |
1 |
100.00 |
|
|
aon_timer_csr_aliasing |
2.810s |
511.244us |
1 |
1 |
100.00 |
|
|
aon_timer_same_csr_outstanding |
2.870s |
890.264us |
1 |
1 |
100.00 |
| V2 |
tl_d_partial_access |
aon_timer_csr_hw_reset |
2.320s |
1.225ms |
1 |
1 |
100.00 |
|
|
aon_timer_csr_rw |
1.620s |
424.565us |
1 |
1 |
100.00 |
|
|
aon_timer_csr_aliasing |
2.810s |
511.244us |
1 |
1 |
100.00 |
|
|
aon_timer_same_csr_outstanding |
2.870s |
890.264us |
1 |
1 |
100.00 |
| V2 |
|
TOTAL |
|
|
7 |
7 |
100.00 |
| V2S |
tl_intg_err |
aon_timer_sec_cm |
6.290s |
8.128ms |
1 |
1 |
100.00 |
|
|
aon_timer_tl_intg_err |
6.850s |
8.056ms |
1 |
1 |
100.00 |
| V2S |
sec_cm_bus_integrity |
aon_timer_tl_intg_err |
6.850s |
8.056ms |
1 |
1 |
100.00 |
| V2S |
|
TOTAL |
|
|
2 |
2 |
100.00 |
| V3 |
max_threshold |
aon_timer_smoke_max_thold |
2.270s |
600.650us |
1 |
1 |
100.00 |
| V3 |
min_threshold |
aon_timer_smoke_min_thold |
2.520s |
633.944us |
1 |
1 |
100.00 |
| V3 |
wkup_count_hi_cdc |
aon_timer_wkup_count_cdc_hi |
3.240s |
3.572ms |
1 |
1 |
100.00 |
| V3 |
custom_intr |
aon_timer_custom_intr |
1.660s |
775.273us |
1 |
1 |
100.00 |
| V3 |
alternating_on_off |
aon_timer_alternating_enable_on_off |
4.710s |
4.054ms |
1 |
1 |
100.00 |
| V3 |
stress_all_with_rand_reset |
aon_timer_stress_all_with_rand_reset |
6.890s |
1.473ms |
1 |
1 |
100.00 |
| V3 |
|
TOTAL |
|
|
6 |
6 |
100.00 |
|
|
TOTAL |
|
|
23 |
23 |
100.00 |