EDN Simulation Results

Monday May 12 2025 18:42:29 UTC

GitHub Revision: 4f742bf

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	edn_smoke	1.820s	17.235us	1	1	100.00
V1	csr_hw_reset	edn_csr_hw_reset	1.650s	14.269us	1	1	100.00
V1	csr_rw	edn_csr_rw	1.570s	33.607us	1	1	100.00
V1	csr_bit_bash	edn_csr_bit_bash	5.260s	260.592us	1	1	100.00
V1	csr_aliasing	edn_csr_aliasing	1.820s	19.513us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	edn_csr_mem_rw_with_rand_reset	1.810s	41.276us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	edn_csr_rw	1.570s	33.607us	1	1	100.00
		edn_csr_aliasing	1.820s	19.513us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	firmware	edn_genbits	2.370s	51.940us	1	1	100.00
V2	csrng_commands	edn_genbits	2.370s	51.940us	1	1	100.00
V2	genbits	edn_genbits	2.370s	51.940us	1	1	100.00
V2	interrupts	edn_intr	1.920s	21.828us	1	1	100.00
V2	alerts	edn_alert	1.880s	50.819us	1	1	100.00
V2	errs	edn_err	1.840s	21.401us	1	1	100.00
V2	disable	edn_disable	1.680s	35.828us	1	1	100.00
		edn_disable_auto_req_mode	1.900s	28.316us	1	1	100.00
V2	stress_all	edn_stress_all	5.340s	311.489us	1	1	100.00
V2	intr_test	edn_intr_test	1.920s	39.717us	1	1	100.00
V2	alert_test	edn_alert_test	1.760s	14.542us	1	1	100.00
V2	tl_d_oob_addr_access	edn_tl_errors	3.060s	134.771us	1	1	100.00
V2	tl_d_illegal_access	edn_tl_errors	3.060s	134.771us	1	1	100.00
V2	tl_d_outstanding_access	edn_csr_hw_reset	1.650s	14.269us	1	1	100.00
		edn_csr_rw	1.570s	33.607us	1	1	100.00
		edn_csr_aliasing	1.820s	19.513us	1	1	100.00
		edn_same_csr_outstanding	2.060s	118.661us	1	1	100.00
V2	tl_d_partial_access	edn_csr_hw_reset	1.650s	14.269us	1	1	100.00
		edn_csr_rw	1.570s	33.607us	1	1	100.00
		edn_csr_aliasing	1.820s	19.513us	1	1	100.00
		edn_same_csr_outstanding	2.060s	118.661us	1	1	100.00
V2		TOTAL			11	11	100.00
V2S	tl_intg_err	edn_sec_cm	6.040s	453.500us	1	1	100.00
		edn_tl_intg_err	3.630s	145.462us	1	1	100.00
V2S	sec_cm_config_regwen	edn_regwen	1.680s	22.475us	1	1	100.00
V2S	sec_cm_config_mubi	edn_alert	1.880s	50.819us	1	1	100.00
V2S	sec_cm_main_sm_fsm_sparse	edn_sec_cm	6.040s	453.500us	1	1	100.00
V2S	sec_cm_ack_sm_fsm_sparse	edn_sec_cm	6.040s	453.500us	1	1	100.00
V2S	sec_cm_fifo_ctr_redun	edn_sec_cm	6.040s	453.500us	1	1	100.00
V2S	sec_cm_ctr_redun	edn_sec_cm	6.040s	453.500us	1	1	100.00
V2S	sec_cm_main_sm_ctr_local_esc	edn_alert	1.880s	50.819us	1	1	100.00
		edn_sec_cm	6.040s	453.500us	1	1	100.00
V2S	sec_cm_cs_rdata_bus_consistency	edn_alert	1.880s	50.819us	1	1	100.00
V2S	sec_cm_tile_link_bus_integrity	edn_tl_intg_err	3.630s	145.462us	1	1	100.00
V2S		TOTAL			3	3	100.00
V3	stress_all_with_rand_reset	edn_stress_all_with_rand_reset	48.270s	23.117ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			21	21	100.00