HMAC Simulation Results

Monday May 12 2025 18:42:29 UTC

GitHub Revision: 4f742bf

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke hmac_smoke 5.020s 272.944us 1 1 100.00
V1 csr_hw_reset hmac_csr_hw_reset 2.060s 30.896us 1 1 100.00
V1 csr_rw hmac_csr_rw 1.880s 34.200us 1 1 100.00
V1 csr_bit_bash hmac_csr_bit_bash 10.750s 2.543ms 1 1 100.00
V1 csr_aliasing hmac_csr_aliasing 3.120s 435.035us 1 1 100.00
V1 csr_mem_rw_with_rand_reset hmac_csr_mem_rw_with_rand_reset 9.498m 612.850ms 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr hmac_csr_rw 1.880s 34.200us 1 1 100.00
hmac_csr_aliasing 3.120s 435.035us 1 1 100.00
V1 TOTAL 6 6 100.00
V2 long_msg hmac_long_msg 20.780s 2.667ms 1 1 100.00
V2 back_pressure hmac_back_pressure 57.630s 1.406ms 1 1 100.00
V2 test_vectors hmac_test_sha256_vectors 9.650s 340.962us 1 1 100.00
hmac_test_sha384_vectors 6.356m 45.670ms 1 1 100.00
hmac_test_sha512_vectors 5.806m 19.771ms 1 1 100.00
hmac_test_hmac256_vectors 6.630s 201.815us 1 1 100.00
hmac_test_hmac384_vectors 9.830s 4.145ms 1 1 100.00
hmac_test_hmac512_vectors 11.370s 1.316ms 1 1 100.00
V2 burst_wr hmac_burst_wr 3.430s 46.668us 1 1 100.00
V2 datapath_stress hmac_datapath_stress 2.059m 1.926ms 1 1 100.00
V2 error hmac_error 1.108m 17.952ms 1 1 100.00
V2 wipe_secret hmac_wipe_secret 1.324m 12.100ms 1 1 100.00
V2 save_and_restore hmac_smoke 5.020s 272.944us 1 1 100.00
hmac_long_msg 20.780s 2.667ms 1 1 100.00
hmac_back_pressure 57.630s 1.406ms 1 1 100.00
hmac_datapath_stress 2.059m 1.926ms 1 1 100.00
hmac_burst_wr 3.430s 46.668us 1 1 100.00
hmac_stress_all 8.370m 75.182ms 1 1 100.00
V2 fifo_empty_status_interrupt hmac_smoke 5.020s 272.944us 1 1 100.00
hmac_long_msg 20.780s 2.667ms 1 1 100.00
hmac_back_pressure 57.630s 1.406ms 1 1 100.00
hmac_datapath_stress 2.059m 1.926ms 1 1 100.00
hmac_wipe_secret 1.324m 12.100ms 1 1 100.00
hmac_test_sha256_vectors 9.650s 340.962us 1 1 100.00
hmac_test_sha384_vectors 6.356m 45.670ms 1 1 100.00
hmac_test_sha512_vectors 5.806m 19.771ms 1 1 100.00
hmac_test_hmac256_vectors 6.630s 201.815us 1 1 100.00
hmac_test_hmac384_vectors 9.830s 4.145ms 1 1 100.00
hmac_test_hmac512_vectors 11.370s 1.316ms 1 1 100.00
V2 wide_digest_configurable_key_length hmac_smoke 5.020s 272.944us 1 1 100.00
hmac_long_msg 20.780s 2.667ms 1 1 100.00
hmac_back_pressure 57.630s 1.406ms 1 1 100.00
hmac_datapath_stress 2.059m 1.926ms 1 1 100.00
hmac_burst_wr 3.430s 46.668us 1 1 100.00
hmac_error 1.108m 17.952ms 1 1 100.00
hmac_wipe_secret 1.324m 12.100ms 1 1 100.00
hmac_test_sha256_vectors 9.650s 340.962us 1 1 100.00
hmac_test_sha384_vectors 6.356m 45.670ms 1 1 100.00
hmac_test_sha512_vectors 5.806m 19.771ms 1 1 100.00
hmac_test_hmac256_vectors 6.630s 201.815us 1 1 100.00
hmac_test_hmac384_vectors 9.830s 4.145ms 1 1 100.00
hmac_test_hmac512_vectors 11.370s 1.316ms 1 1 100.00
hmac_stress_all 8.370m 75.182ms 1 1 100.00
V2 stress_all hmac_stress_all 8.370m 75.182ms 1 1 100.00
V2 alert_test hmac_alert_test 1.440s 10.859us 1 1 100.00
V2 intr_test hmac_intr_test 1.560s 13.271us 1 1 100.00
V2 tl_d_oob_addr_access hmac_tl_errors 2.570s 31.333us 1 1 100.00
V2 tl_d_illegal_access hmac_tl_errors 2.570s 31.333us 1 1 100.00
V2 tl_d_outstanding_access hmac_csr_hw_reset 2.060s 30.896us 1 1 100.00
hmac_csr_rw 1.880s 34.200us 1 1 100.00
hmac_csr_aliasing 3.120s 435.035us 1 1 100.00
hmac_same_csr_outstanding 2.410s 392.469us 1 1 100.00
V2 tl_d_partial_access hmac_csr_hw_reset 2.060s 30.896us 1 1 100.00
hmac_csr_rw 1.880s 34.200us 1 1 100.00
hmac_csr_aliasing 3.120s 435.035us 1 1 100.00
hmac_same_csr_outstanding 2.410s 392.469us 1 1 100.00
V2 TOTAL 17 17 100.00
V2S tl_intg_err hmac_sec_cm 2.330s 125.598us 1 1 100.00
hmac_tl_intg_err 3.130s 714.814us 1 1 100.00
V2S sec_cm_bus_integrity hmac_tl_intg_err 3.130s 714.814us 1 1 100.00
V2S TOTAL 2 2 100.00
V3 write_config_and_secret_key_during_msg_wr hmac_smoke 5.020s 272.944us 1 1 100.00
V3 stress_reset hmac_stress_reset 2.080s 61.862us 1 1 100.00
V3 stress_all_with_rand_reset hmac_stress_all_with_rand_reset 1.634m 16.671ms 1 1 100.00
V3 TOTAL 2 2 100.00
Unmapped tests hmac_directed 4.300s 181.991us 1 1 100.00
TOTAL 28 28 100.00