I2C Simulation Results

Monday May 12 2025 18:42:29 UTC

GitHub Revision: `4f742bf`

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	host_smoke	i2c_host_smoke	1.076m	8.638ms	1	1	100.00
V1	target_smoke	i2c_target_smoke	10.790s	1.321ms	1	1	100.00
V1	csr_hw_reset	i2c_csr_hw_reset	1.530s	19.627us	1	1	100.00
V1	csr_rw	i2c_csr_rw	1.660s	57.181us	1	1	100.00
V1	csr_bit_bash	i2c_csr_bit_bash	4.760s	2.175ms	1	1	100.00
V1	csr_aliasing	i2c_csr_aliasing	2.490s	171.426us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	i2c_csr_mem_rw_with_rand_reset	1.840s	52.115us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	i2c_csr_rw	1.660s	57.181us	1	1	100.00
		i2c_csr_aliasing	2.490s	171.426us	1	1	100.00
V1		TOTAL			7	7	100.00
V2	host_error_intr	i2c_host_error_intr	3.390s	187.465us	1	1	100.00
V2	host_stress_all	i2c_host_stress_all	6.200m	57.470ms	0	1	0.00
V2	host_maxperf	i2c_host_perf	46.950s	6.911ms	1	1	100.00
V2	host_override	i2c_host_override	1.590s	52.327us	1	1	100.00
V2	host_fifo_watermark	i2c_host_fifo_watermark	1.577m	5.068ms	1	1	100.00
V2	host_fifo_overflow	i2c_host_fifo_overflow	1.174m	1.747ms	1	1	100.00
V2	host_fifo_reset	i2c_host_fifo_reset_fmt	1.830s	696.131us	1	1	100.00
		i2c_host_fifo_fmt_empty	19.610s	976.182us	1	1	100.00
		i2c_host_fifo_reset_rx	4.040s	569.928us	1	1	100.00
V2	host_fifo_full	i2c_host_fifo_full	2.229m	13.110ms	1	1	100.00
V2	host_timeout	i2c_host_stretch_timeout	21.810s	1.211ms	1	1	100.00
V2	i2c_host_mode_toggle	i2c_host_mode_toggle	3.230s	292.254us	0	1	0.00
V2	target_glitch	i2c_target_glitch	14.510s	8.016ms	1	1	100.00
V2	target_stress_all	i2c_target_stress_all	1.986m	18.323ms	1	1	100.00
V2	target_maxperf	i2c_target_perf	4.730s	3.119ms	1	1	100.00
V2	target_fifo_empty	i2c_target_stress_rd	14.030s	5.001ms	1	1	100.00
		i2c_target_intr_smoke	9.760s	5.147ms	1	1	100.00
V2	target_fifo_reset	i2c_target_fifo_reset_acq	1.670s	305.971us	1	1	100.00
		i2c_target_fifo_reset_tx	1.640s	136.669us	1	1	100.00
V2	target_fifo_full	i2c_target_stress_wr	1.103m	24.269ms	1	1	100.00
		i2c_target_stress_rd	14.030s	5.001ms	1	1	100.00
		i2c_target_intr_stress_wr	1.222m	19.433ms	1	1	100.00
V2	target_timeout	i2c_target_timeout	5.110s	5.521ms	1	1	100.00
V2	target_clock_stretch	i2c_target_stretch	17.130s	3.714ms	1	1	100.00
V2	bad_address	i2c_target_bad_addr	4.740s	2.374ms	1	1	100.00
V2	target_mode_glitch	i2c_target_hrst	6.170s	10.527ms	0	1	0.00
V2	target_fifo_watermark	i2c_target_fifo_watermarks_acq	3.410s	459.594us	1	1	100.00
		i2c_target_fifo_watermarks_tx	2.360s	110.679us	1	1	100.00
V2	host_mode_config_perf	i2c_host_perf	46.950s	6.911ms	1	1	100.00
		i2c_host_perf_precise	2.530s	134.669us	1	1	100.00
V2	host_mode_clock_stretching	i2c_host_stretch_timeout	21.810s	1.211ms	1	1	100.00
V2	target_mode_tx_stretch_ctrl	i2c_target_tx_stretch_ctrl	7.850s	752.243us	1	1	100.00
V2	target_mode_nack_generation	i2c_target_nack_acqfull	3.200s	3.063ms	1	1	100.00
		i2c_target_nack_acqfull_addr	2.630s	399.628us	1	1	100.00
		i2c_target_nack_txstretch	2.270s	869.602us	1	1	100.00
V2	host_mode_halt_on_nak	i2c_host_may_nack	10.140s	313.611us	1	1	100.00
V2	target_mode_smbus_maxlen	i2c_target_smbus_maxlen	2.630s	1.673ms	1	1	100.00
V2	alert_test	i2c_alert_test	1.600s	48.270us	1	1	100.00
V2	intr_test	i2c_intr_test	1.640s	19.664us	1	1	100.00
V2	tl_d_oob_addr_access	i2c_tl_errors	3.290s	51.240us	1	1	100.00
V2	tl_d_illegal_access	i2c_tl_errors	3.290s	51.240us	1	1	100.00
V2	tl_d_outstanding_access	i2c_csr_hw_reset	1.530s	19.627us	1	1	100.00
		i2c_csr_rw	1.660s	57.181us	1	1	100.00
		i2c_csr_aliasing	2.490s	171.426us	1	1	100.00
		i2c_same_csr_outstanding	1.780s	38.102us	1	1	100.00
V2	tl_d_partial_access	i2c_csr_hw_reset	1.530s	19.627us	1	1	100.00
		i2c_csr_rw	1.660s	57.181us	1	1	100.00
		i2c_csr_aliasing	2.490s	171.426us	1	1	100.00
		i2c_same_csr_outstanding	1.780s	38.102us	1	1	100.00
V2		TOTAL			35	38	92.11
V2S	tl_intg_err	i2c_tl_intg_err	2.820s	182.988us	1	1	100.00
		i2c_sec_cm	1.680s	212.628us	1	1	100.00
V2S	sec_cm_bus_integrity	i2c_tl_intg_err	2.820s	182.988us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	host_stress_all_with_rand_reset	i2c_host_stress_all_with_rand_reset	9.640s	1.100ms	0	1	0.00
V3	target_error_intr	i2c_target_unexp_stop	1.590s	62.672us	0	1	0.00
V3	target_stress_all_with_rand_reset	i2c_target_stress_all_with_rand_reset	18.880s	13.687ms	0	1	0.00
V3		TOTAL			0	3	0.00
		TOTAL			44	50	88.00

Failure Buckets

UVM_ERROR (i2c_scoreboard.sv:716) [scoreboard] controller_mode_rd_obs_fifo item uncompared: has 2 failures:

Test i2c_host_stress_all has 1 failures.

0.i2c_host_stress_all.64393708904452759038399695366482089870981718376731293327018358768688902811935
Line 188, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_host_stress_all/latest/run.log

  UVM_ERROR @ 57470335374 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
  ----------------------------------------------------
  Name            Type                Size  Value
  ----------------------------------------------------
  mon_dut_item    i2c_item            -     @10826144

Test i2c_host_mode_toggle has 1 failures.

0.i2c_host_mode_toggle.115357090988412890991979365327481970881511326979938963379452592107738877005536
Line 80, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_host_mode_toggle/latest/run.log

  UVM_ERROR @ 292254167 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
  ----------------------------------------------------
  Name            Type                Size  Value
  ----------------------------------------------------
  mon_dut_item    i2c_item            -     @28247

UVM_ERROR (cip_base_vseq.sv:928) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 2 failures:
- Test i2c_host_stress_all_with_rand_reset has 1 failures.
  - 0.i2c_host_stress_all_with_rand_reset.14259062158377578133941667781251723815832492494590025614236925012440362287316
    Line 91, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_host_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1099619733 ps: (cip_base_vseq.sv:928) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 1099619733 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test i2c_target_stress_all_with_rand_reset has 1 failures.
  - 0.i2c_target_stress_all_with_rand_reset.110062102989596913268652682742551526263696353697178788770632356391840811530841
    Line 143, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_target_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 13687205793 ps: (cip_base_vseq.sv:928) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 13687205793 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (i2c_base_vseq.sv:1474) [i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (* [*] vs * [*]) has 1 failures:
- Test i2c_target_unexp_stop has 1 failures.
  - 0.i2c_target_unexp_stop.14723504261237710640836085003857518909283271086661992845517430219715110040912
    Line 73, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_target_unexp_stop/latest/run.log
```
  UVM_ERROR @  62671890 ps: (i2c_base_vseq.sv:1474) [uvm_test_top.env.virtual_sequencer.i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (0 [0x0] vs 1 [0x1])
  UVM_INFO @  62671890 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred! has 1 failures:
- Test i2c_target_hrst has 1 failures.
  - 0.i2c_target_hrst.13978455297038105844502286427582299664048783115051574788237430824099371219454
    Line 74, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_target_hrst/latest/run.log
```
  UVM_FATAL @ 10526968134 ps: (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred!
  UVM_INFO @ 10526968134 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```