KMAC/MASKED Simulation Results

Monday May 12 2025 18:42:29 UTC

GitHub Revision: 4f742bf

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	40.010s	4.276ms	1	1	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	2.030s	63.538us	1	1	100.00
V1	csr_rw	kmac_csr_rw	1.970s	34.881us	1	1	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	15.180s	3.192ms	1	1	100.00
V1	csr_aliasing	kmac_csr_aliasing	6.310s	152.687us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	3.350s	125.950us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	1.970s	34.881us	1	1	100.00
		kmac_csr_aliasing	6.310s	152.687us	1	1	100.00
V1	mem_walk	kmac_mem_walk	1.510s	34.043us	1	1	100.00
V1	mem_partial_access	kmac_mem_partial_access	2.420s	58.136us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	38.519m	72.358ms	1	1	100.00
V2	burst_write	kmac_burst_write	9.286m	114.643ms	1	1	100.00
V2	test_vectors	kmac_test_vectors_sha3_224	38.730s	15.823ms	1	1	100.00
		kmac_test_vectors_sha3_256	21.912m	17.298ms	1	1	100.00
		kmac_test_vectors_sha3_384	24.110s	7.712ms	1	1	100.00
		kmac_test_vectors_sha3_512	12.770s	2.131ms	1	1	100.00
		kmac_test_vectors_shake_128	1.951m	17.763ms	1	1	100.00
		kmac_test_vectors_shake_256	30.750m	269.220ms	1	1	100.00
		kmac_test_vectors_kmac	3.730s	415.614us	1	1	100.00
		kmac_test_vectors_kmac_xof	3.610s	111.469us	1	1	100.00
V2	sideload	kmac_sideload	4.075m	52.081ms	1	1	100.00
V2	app	kmac_app	2.825m	35.978ms	1	1	100.00
V2	app_with_partial_data	kmac_app_with_partial_data	1.541m	2.679ms	1	1	100.00
V2	entropy_refresh	kmac_entropy_refresh	54.060s	6.386ms	1	1	100.00
V2	error	kmac_error	14.230s	252.534us	1	1	100.00
V2	key_error	kmac_key_error	6.210s	2.141ms	1	1	100.00
V2	sideload_invalid	kmac_sideload_invalid	6.400s	105.801us	1	1	100.00
V2	edn_timeout_error	kmac_edn_timeout_error	32.690s	669.523us	1	1	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	2.030s	63.575us	1	1	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	39.900s	18.700ms	1	1	100.00
V2	lc_escalation	kmac_lc_escalation	11.930s	1.813ms	1	1	100.00
V2	stress_all	kmac_stress_all	4.249m	22.411ms	1	1	100.00
V2	intr_test	kmac_intr_test	1.710s	24.917us	1	1	100.00
V2	alert_test	kmac_alert_test	1.820s	66.849us	1	1	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	2.370s	70.695us	1	1	100.00
V2	tl_d_illegal_access	kmac_tl_errors	2.370s	70.695us	1	1	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	2.030s	63.538us	1	1	100.00
		kmac_csr_rw	1.970s	34.881us	1	1	100.00
		kmac_csr_aliasing	6.310s	152.687us	1	1	100.00
		kmac_same_csr_outstanding	2.600s	184.543us	1	1	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	2.030s	63.538us	1	1	100.00
		kmac_csr_rw	1.970s	34.881us	1	1	100.00
		kmac_csr_aliasing	6.310s	152.687us	1	1	100.00
		kmac_same_csr_outstanding	2.600s	184.543us	1	1	100.00
V2		TOTAL			26	26	100.00
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	2.360s	167.308us	1	1	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	2.360s	167.308us	1	1	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	2.360s	167.308us	1	1	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	2.360s	167.308us	1	1	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	3.870s	286.840us	1	1	100.00
V2S	tl_intg_err	kmac_sec_cm	35.070s	15.102ms	1	1	100.00
		kmac_tl_intg_err	4.240s	201.217us	1	1	100.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	4.240s	201.217us	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	11.930s	1.813ms	1	1	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	40.010s	4.276ms	1	1	100.00
V2S	sec_cm_key_sideload	kmac_sideload	4.075m	52.081ms	1	1	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	2.360s	167.308us	1	1	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	35.070s	15.102ms	1	1	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	35.070s	15.102ms	1	1	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	35.070s	15.102ms	1	1	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	40.010s	4.276ms	1	1	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	11.930s	1.813ms	1	1	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	35.070s	15.102ms	1	1	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	32.610s	1.436ms	1	1	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	40.010s	4.276ms	1	1	100.00
V2S		TOTAL			5	5	100.00
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	2.660s	127.242us	0	1	0.00
V3		TOTAL			0	1	0.00
		TOTAL			39	40	97.50

Failure Buckets

• UVM_ERROR (kmac_scoreboard.sv:1202) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: kmac_reg_block.err_code has 1 failures:
  • Test kmac_stress_all_with_rand_reset has 1 failures.

    • 0.kmac_stress_all_with_rand_reset.113972329543180082971047804937326556307166413845158165229028402743996630583040
      Line 91, in log /nightly/runs/scratch/master/kmac_masked-sim-vcs/0.kmac_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 127242200 ps: (kmac_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483768 [0x80000078]) reg name: kmac_reg_block.err_code
        UVM_INFO @ 127242200 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---