KMAC/UNMASKED Simulation Results

Monday May 12 2025 18:42:29 UTC

GitHub Revision: 4f742bf

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	6.600s	742.293us	1	1	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	1.790s	42.055us	1	1	100.00
V1	csr_rw	kmac_csr_rw	1.930s	25.514us	1	1	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	13.130s	985.326us	1	1	100.00
V1	csr_aliasing	kmac_csr_aliasing	5.950s	137.339us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	2.860s	310.098us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	1.930s	25.514us	1	1	100.00
		kmac_csr_aliasing	5.950s	137.339us	1	1	100.00
V1	mem_walk	kmac_mem_walk	1.630s	12.988us	1	1	100.00
V1	mem_partial_access	kmac_mem_partial_access	1.780s	31.728us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	4.041m	16.580ms	1	1	100.00
V2	burst_write	kmac_burst_write	6.659m	6.472ms	1	1	100.00
V2	test_vectors	kmac_test_vectors_sha3_224	17.907m	141.690ms	1	1	100.00
		kmac_test_vectors_sha3_256	28.280s	3.602ms	1	1	100.00
		kmac_test_vectors_sha3_384	15.690s	1.641ms	1	1	100.00
		kmac_test_vectors_sha3_512	14.209m	189.474ms	1	1	100.00
		kmac_test_vectors_shake_128	20.427m	85.055ms	1	1	100.00
		kmac_test_vectors_shake_256	27.834m	524.442ms	1	1	100.00
		kmac_test_vectors_kmac	2.880s	59.007us	1	1	100.00
		kmac_test_vectors_kmac_xof	2.530s	32.174us	1	1	100.00
V2	sideload	kmac_sideload	1.466m	1.631ms	1	1	100.00
V2	app	kmac_app	4.180s	105.307us	1	1	100.00
V2	app_with_partial_data	kmac_app_with_partial_data	1.924m	16.815ms	1	1	100.00
V2	entropy_refresh	kmac_entropy_refresh	2.062m	9.474ms	1	1	100.00
V2	error	kmac_error	17.390s	1.106ms	1	1	100.00
V2	key_error	kmac_key_error	6.640s	6.377ms	1	1	100.00
V2	sideload_invalid	kmac_sideload_invalid	4.800s	162.725us	1	1	100.00
V2	edn_timeout_error	kmac_edn_timeout_error	18.280s	1.502ms	1	1	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	19.620s	425.646us	1	1	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	41.860s	3.217ms	1	1	100.00
V2	lc_escalation	kmac_lc_escalation	2.240s	29.092us	1	1	100.00
V2	stress_all	kmac_stress_all	2.019m	16.661ms	1	1	100.00
V2	intr_test	kmac_intr_test	1.520s	27.458us	1	1	100.00
V2	alert_test	kmac_alert_test	1.650s	55.710us	1	1	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	2.360s	73.493us	1	1	100.00
V2	tl_d_illegal_access	kmac_tl_errors	2.360s	73.493us	1	1	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	1.790s	42.055us	1	1	100.00
		kmac_csr_rw	1.930s	25.514us	1	1	100.00
		kmac_csr_aliasing	5.950s	137.339us	1	1	100.00
		kmac_same_csr_outstanding	2.990s	171.756us	1	1	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	1.790s	42.055us	1	1	100.00
		kmac_csr_rw	1.930s	25.514us	1	1	100.00
		kmac_csr_aliasing	5.950s	137.339us	1	1	100.00
		kmac_same_csr_outstanding	2.990s	171.756us	1	1	100.00
V2		TOTAL			26	26	100.00
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	2.040s	211.919us	1	1	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	2.040s	211.919us	1	1	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	2.040s	211.919us	1	1	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	2.040s	211.919us	1	1	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	1.920s	96.383us	0	1	0.00
V2S	tl_intg_err	kmac_sec_cm	35.480s	14.249ms	1	1	100.00
		kmac_tl_intg_err	2.880s	135.656us	1	1	100.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	2.880s	135.656us	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	2.240s	29.092us	1	1	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	6.600s	742.293us	1	1	100.00
V2S	sec_cm_key_sideload	kmac_sideload	1.466m	1.631ms	1	1	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	2.040s	211.919us	1	1	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	35.480s	14.249ms	1	1	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	35.480s	14.249ms	1	1	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	35.480s	14.249ms	1	1	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	6.600s	742.293us	1	1	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	2.240s	29.092us	1	1	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	35.480s	14.249ms	1	1	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	33.580s	2.033ms	1	1	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	6.600s	742.293us	1	1	100.00
V2S		TOTAL			4	5	80.00
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	31.890s	8.654ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			39	40	97.50

Failure Buckets

• Offending '(d2h.d_error || ((d2h.d_data & *) == (exp_vals[*] & *)))' has 1 failures:
  • Test kmac_shadow_reg_errors_with_csr_rw has 1 failures.

    • 0.kmac_shadow_reg_errors_with_csr_rw.65596693488188819746567409918830841139933212034344581491208338550250376404056
      Line 86, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/0.kmac_shadow_reg_errors_with_csr_rw/latest/run.log

            Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[42] & 'hffffffff)))'
        UVM_ERROR @  96382719 ps: (kmac_csr_assert_fpv.sv:507) [ASSERT FAILED] prefix_3_rd_A
        UVM_INFO @  96382719 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---