OTBN Simulation Results

Monday May 12 2025 18:42:29 UTC

GitHub Revision: 4f742bf

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	otbn_smoke	13.000s	144.979us	1	1	100.00
V1	single_binary	otbn_single	15.000s	50.294us	1	1	100.00
V1	csr_hw_reset	otbn_csr_hw_reset	6.000s	36.012us	1	1	100.00
V1	csr_rw	otbn_csr_rw	5.000s	13.337us	1	1	100.00
V1	csr_bit_bash	otbn_csr_bit_bash	7.000s	164.632us	1	1	100.00
V1	csr_aliasing	otbn_csr_aliasing	6.000s	47.794us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	otbn_csr_mem_rw_with_rand_reset	8.000s	67.337us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	otbn_csr_rw	5.000s	13.337us	1	1	100.00
		otbn_csr_aliasing	6.000s	47.794us	1	1	100.00
V1	mem_walk	otbn_mem_walk	11.000s	509.236us	1	1	100.00
V1	mem_partial_access	otbn_mem_partial_access	9.000s	186.606us	1	1	100.00
V1		TOTAL			9	9	100.00
V2	reset_recovery	otbn_reset	37.000s	201.107us	1	1	100.00
V2	multi_error	otbn_multi_err	44.000s	319.691us	1	1	100.00
V2	back_to_back	otbn_multi	7.235s		0	1	0.00
V2	stress_all	otbn_stress_all	1.100m	1.219ms	1	1	100.00
V2	lc_escalation	otbn_escalate	10.000s	116.313us	1	1	100.00
V2	zero_state_err_urnd	otbn_zero_state_err_urnd	8.000s	28.497us	1	1	100.00
V2	sw_errs_fatal_chk	otbn_sw_errs_fatal_chk	18.000s	110.377us	1	1	100.00
V2	alert_test	otbn_alert_test	6.000s	23.343us	1	1	100.00
V2	intr_test	otbn_intr_test	6.000s	14.603us	1	1	100.00
V2	tl_d_oob_addr_access	otbn_tl_errors	6.000s	246.082us	1	1	100.00
V2	tl_d_illegal_access	otbn_tl_errors	6.000s	246.082us	1	1	100.00
V2	tl_d_outstanding_access	otbn_csr_hw_reset	6.000s	36.012us	1	1	100.00
		otbn_csr_rw	5.000s	13.337us	1	1	100.00
		otbn_csr_aliasing	6.000s	47.794us	1	1	100.00
		otbn_same_csr_outstanding	6.000s	81.629us	1	1	100.00
V2	tl_d_partial_access	otbn_csr_hw_reset	6.000s	36.012us	1	1	100.00
		otbn_csr_rw	5.000s	13.337us	1	1	100.00
		otbn_csr_aliasing	6.000s	47.794us	1	1	100.00
		otbn_same_csr_outstanding	6.000s	81.629us	1	1	100.00
V2		TOTAL			10	11	90.91
V2S	mem_integrity	otbn_imem_err	8.000s	50.625us	1	1	100.00
		otbn_dmem_err	12.000s	25.795us	1	1	100.00
V2S	internal_integrity	otbn_alu_bignum_mod_err	14.000s	233.749us	1	1	100.00
		otbn_controller_ispr_rdata_err	9.000s	29.724us	1	1	100.00
		otbn_mac_bignum_acc_err	9.000s	111.874us	1	1	100.00
		otbn_urnd_err	7.000s	24.572us	1	1	100.00
V2S	illegal_bus_access	otbn_illegal_mem_acc	7.000s	152.292us	1	1	100.00
V2S	otbn_mem_gnt_acc_err	otbn_mem_gnt_acc_err	8.000s	106.285us	1	1	100.00
V2S	otbn_non_sec_partial_wipe	otbn_partial_wipe	8.000s	26.842us	1	1	100.00
V2S	tl_intg_err	otbn_sec_cm	1.583m	2.879ms	1	1	100.00
		otbn_tl_intg_err	11.000s	249.856us	1	1	100.00
V2S	passthru_mem_tl_intg_err	otbn_passthru_mem_tl_intg_err	13.000s	392.938us	1	1	100.00
V2S	prim_fsm_check	otbn_sec_cm	1.583m	2.879ms	1	1	100.00
V2S	prim_count_check	otbn_sec_cm	1.583m	2.879ms	1	1	100.00
V2S	sec_cm_mem_scramble	otbn_smoke	13.000s	144.979us	1	1	100.00
V2S	sec_cm_data_mem_integrity	otbn_dmem_err	12.000s	25.795us	1	1	100.00
V2S	sec_cm_instruction_mem_integrity	otbn_imem_err	8.000s	50.625us	1	1	100.00
V2S	sec_cm_bus_integrity	otbn_tl_intg_err	11.000s	249.856us	1	1	100.00
V2S	sec_cm_controller_fsm_global_esc	otbn_escalate	10.000s	116.313us	1	1	100.00
V2S	sec_cm_controller_fsm_local_esc	otbn_imem_err	8.000s	50.625us	1	1	100.00
		otbn_dmem_err	12.000s	25.795us	1	1	100.00
		otbn_zero_state_err_urnd	8.000s	28.497us	1	1	100.00
		otbn_illegal_mem_acc	7.000s	152.292us	1	1	100.00
		otbn_sec_cm	1.583m	2.879ms	1	1	100.00
V2S	sec_cm_controller_fsm_sparse	otbn_sec_cm	1.583m	2.879ms	1	1	100.00
V2S	sec_cm_scramble_key_sideload	otbn_single	15.000s	50.294us	1	1	100.00
V2S	sec_cm_scramble_ctrl_fsm_local_esc	otbn_imem_err	8.000s	50.625us	1	1	100.00
		otbn_dmem_err	12.000s	25.795us	1	1	100.00
		otbn_zero_state_err_urnd	8.000s	28.497us	1	1	100.00
		otbn_illegal_mem_acc	7.000s	152.292us	1	1	100.00
		otbn_sec_cm	1.583m	2.879ms	1	1	100.00
V2S	sec_cm_scramble_ctrl_fsm_sparse	otbn_sec_cm	1.583m	2.879ms	1	1	100.00
V2S	sec_cm_start_stop_ctrl_fsm_global_esc	otbn_escalate	10.000s	116.313us	1	1	100.00
V2S	sec_cm_start_stop_ctrl_fsm_local_esc	otbn_imem_err	8.000s	50.625us	1	1	100.00
		otbn_dmem_err	12.000s	25.795us	1	1	100.00
		otbn_zero_state_err_urnd	8.000s	28.497us	1	1	100.00
		otbn_illegal_mem_acc	7.000s	152.292us	1	1	100.00
		otbn_sec_cm	1.583m	2.879ms	1	1	100.00
V2S	sec_cm_start_stop_ctrl_fsm_sparse	otbn_sec_cm	1.583m	2.879ms	1	1	100.00
V2S	sec_cm_data_reg_sw_sca	otbn_single	15.000s	50.294us	1	1	100.00
V2S	sec_cm_ctrl_redun	otbn_ctrl_redun	8.000s	15.976us	1	1	100.00
V2S	sec_cm_pc_ctrl_flow_redun	otbn_pc_ctrl_flow_redun	7.000s	86.693us	1	1	100.00
V2S	sec_cm_rnd_bus_consistency	otbn_rnd_sec_cm	19.000s	154.214us	1	1	100.00
V2S	sec_cm_rnd_rng_digest	otbn_rnd_sec_cm	19.000s	154.214us	1	1	100.00
V2S	sec_cm_rf_base_data_reg_sw_integrity	otbn_rf_base_intg_err	10.000s	30.219us	1	1	100.00
V2S	sec_cm_rf_base_data_reg_sw_glitch_detect	otbn_sec_cm	1.583m	2.879ms	1	1	100.00
V2S	sec_cm_stack_wr_ptr_ctr_redun	otbn_sec_cm	1.583m	2.879ms	1	1	100.00
V2S	sec_cm_rf_bignum_data_reg_sw_integrity	otbn_rf_bignum_intg_err	10.000s	54.419us	1	1	100.00
V2S	sec_cm_rf_bignum_data_reg_sw_glitch_detect	otbn_sec_cm	1.583m	2.879ms	1	1	100.00
V2S	sec_cm_loop_stack_ctr_redun	otbn_sec_cm	1.583m	2.879ms	1	1	100.00
V2S	sec_cm_loop_stack_addr_integrity	otbn_stack_addr_integ_chk	9.000s	93.274us	1	1	100.00
V2S	sec_cm_call_stack_addr_integrity	otbn_stack_addr_integ_chk	9.000s	93.274us	1	1	100.00
V2S	sec_cm_start_stop_ctrl_state_consistency	otbn_sec_wipe_err	12.000s	170.468us	0	1	0.00
V2S	sec_cm_data_mem_sec_wipe	otbn_single	15.000s	50.294us	1	1	100.00
V2S	sec_cm_instruction_mem_sec_wipe	otbn_single	15.000s	50.294us	1	1	100.00
V2S	sec_cm_data_reg_sw_sec_wipe	otbn_single	15.000s	50.294us	1	1	100.00
V2S	sec_cm_write_mem_integrity	otbn_multi	7.235s		0	1	0.00
V2S	sec_cm_ctrl_flow_count	otbn_single	15.000s	50.294us	1	1	100.00
V2S	sec_cm_ctrl_flow_sca	otbn_single	15.000s	50.294us	1	1	100.00
V2S	sec_cm_data_mem_sw_noaccess	otbn_sw_no_acc	16.000s	55.859us	1	1	100.00
V2S	sec_cm_key_sideload	otbn_single	15.000s	50.294us	1	1	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	otbn_sec_cm	1.583m	2.879ms	1	1	100.00
V2S		TOTAL			19	20	95.00
V3	stress_all_with_rand_reset	otbn_stress_all_with_rand_reset	1.533m	496.025us	0	1	0.00
V3		TOTAL			0	1	0.00
		TOTAL			38	41	92.68

Failure Buckets

• Job returned non-zero exit code has 1 failures:

  • Test otbn_multi has 1 failures.

    • 0.otbn_multi.100443826792049618190802631237232096409651428952492085164675748882660336661833
      Log /nightly/runs/scratch/master/otbn-sim-xcelium/0.otbn_multi/latest/run.log

        make -f /nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='pushd /nightly/runs/opentitan; source hw/ip/otbn/dv/uvm/get-toolchain-paths.sh; popd; /nightly/runs/opentitan/hw/ip/otbn/dv/uvm/gen-binaries.py --seed 100443826792049618190802631237232096409651428952492085164675748882660336661833 --size 2000 --count 10 /nightly/runs/scratch/master/otbn-sim-xcelium/0.otbn_multi/latest/otbn-binaries' proj_root=/nightly/runs/opentitan run_cmd=xrun run_dir=/nightly/runs/scratch/master/otbn-sim-xcelium/0.otbn_multi/latest run_opts='+en_cov=1 -covmodeldir /nightly/runs/scratch/master/otbn-sim-xcelium/coverage/default/0.otbn_multi.603780425 -covworkdir /nightly/runs/scratch/master/otbn-sim-xcelium/coverage -covscope default -covtest 0.otbn_multi.603780425 -covoverwrite +otbn_elf_dir=/nightly/runs/scratch/master/otbn-sim-xcelium/0.otbn_multi/latest/otbn-binaries +cdc_instrumentation_enabled=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/runs/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/runs/scratch/master/otbn-sim-xcelium/default/xcelium.d -r tb +SVSEED=603780425 +UVM_TESTNAME=otbn_base_test +UVM_TEST_SEQ=otbn_multi_vseq -nowarn DSEM2009' seed=100443826792049618190802631237232096409651428952492085164675748882660336661833 sw_build_cmd=bazel sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otbn_base_test uvm_test_seq=otbn_multi_vseq
      
        [make]: pre_run
        mkdir -p /nightly/runs/scratch/master/otbn-sim-xcelium/0.otbn_multi/latest
        cd /nightly/runs/scratch/master/otbn-sim-xcelium/0.otbn_multi/latest && pushd /nightly/runs/opentitan; source hw/ip/otbn/dv/uvm/get-toolchain-paths.sh; popd; /nightly/runs/opentitan/hw/ip/otbn/dv/uvm/gen-binaries.py --seed 100443826792049618190802631237232096409651428952492085164675748882660336661833 --size 2000 --count 10 /nightly/runs/scratch/master/otbn-sim-xcelium/0.otbn_multi/latest/otbn-binaries
        ~/opentitan ~/scratch/master/otbn-sim-xcelium/0.otbn_multi/latest
        2025/05/12 18:59:02 Downloading https://releases.bazel.build/8.0.1/release/bazel-8.0.1-linux-x86_64...
        Opening zip "/nightly/runs/.cache/bazelisk/downloads/sha256/40f243b118f46d1c88842315e78ec5f9f6390980d67a90f7b64098613e60d65b/bin/bazel (deleted)": open(): No such file or directory
        FATAL: Failed to open '/nightly/runs/.cache/bazelisk/downloads/sha256/40f243b118f46d1c88842315e78ec5f9f6390980d67a90f7b64098613e60d65b/bin/bazel (deleted)' as a zip file: (error: 2): No such file or directory
        make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:52: pre_run] Error 36
      

• UVM_ERROR (cip_base_vseq.sv:929) [otbn_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:

  • Test otbn_stress_all_with_rand_reset has 1 failures.

    • 0.otbn_stress_all_with_rand_reset.44060156229777336477865097845670578408491072777233990830398184176152991976235
      Line 171, in log /nightly/runs/scratch/master/otbn-sim-xcelium/0.otbn_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 496024753 ps: (cip_base_vseq.sv:929) [uvm_test_top.env.virtual_sequencer.otbn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 496024753 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• xmsim: *E,ASRTST (/nightly/runs/scratch/master/otbn-sim-xcelium/default/src/lowrisc_dv_otbn_env_*/otbn_insn_cnt_if.sv,21): Assertion InsnCntMatches_A has failed has 1 failures:

  • Test otbn_sec_wipe_err has 1 failures.

    • 0.otbn_sec_wipe_err.46705280281434786189973892241486213307054720975475385833990637034553768373831
      Line 113, in log /nightly/runs/scratch/master/otbn-sim-xcelium/0.otbn_sec_wipe_err/latest/run.log

        xmsim: *E,ASRTST (/nightly/runs/scratch/master/otbn-sim-xcelium/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 170468312 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
        UVM_ERROR @ 170468312 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
        UVM_INFO @ 170468312 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---