PATTGEN Simulation Results

Monday May 12 2025 18:42:29 UTC

GitHub Revision: `4f742bf`

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	pattgen_smoke	12.000s	837.470us	1	1	100.00
V1	csr_hw_reset	pattgen_csr_hw_reset	7.000s	50.047us	1	1	100.00
V1	csr_rw	pattgen_csr_rw	7.000s	75.096us	1	1	100.00
V1	csr_bit_bash	pattgen_csr_bit_bash	7.000s	200.005us	1	1	100.00
V1	csr_aliasing	pattgen_csr_aliasing	3.000s	21.954us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	pattgen_csr_mem_rw_with_rand_reset	4.000s	93.384us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	pattgen_csr_rw	7.000s	75.096us	1	1	100.00
		pattgen_csr_aliasing	3.000s	21.954us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	perf	pattgen_perf	3.317m	45.540ms	1	1	100.00
V2	cnt_rollover	cnt_rollover	19.000s	2.367ms	1	1	100.00
V2	error	pattgen_error	11.000s	27.934us	1	1	100.00
V2	stress_all	pattgen_stress_all	10.000s	327.319us	0	1	0.00
V2	alert_test	pattgen_alert_test	9.000s	37.765us	1	1	100.00
V2	intr_test	pattgen_intr_test	8.000s	15.369us	1	1	100.00
V2	tl_d_oob_addr_access	pattgen_tl_errors	9.000s	426.256us	1	1	100.00
V2	tl_d_illegal_access	pattgen_tl_errors	9.000s	426.256us	1	1	100.00
V2	tl_d_outstanding_access	pattgen_csr_hw_reset	7.000s	50.047us	1	1	100.00
		pattgen_csr_rw	7.000s	75.096us	1	1	100.00
		pattgen_csr_aliasing	3.000s	21.954us	1	1	100.00
		pattgen_same_csr_outstanding	4.000s	34.110us	1	1	100.00
V2	tl_d_partial_access	pattgen_csr_hw_reset	7.000s	50.047us	1	1	100.00
		pattgen_csr_rw	7.000s	75.096us	1	1	100.00
		pattgen_csr_aliasing	3.000s	21.954us	1	1	100.00
		pattgen_same_csr_outstanding	4.000s	34.110us	1	1	100.00
V2		TOTAL			7	8	87.50
V2S	tl_intg_err	pattgen_tl_intg_err	8.000s	155.750us	1	1	100.00
		pattgen_sec_cm	10.000s	75.127us	1	1	100.00
V2S	sec_cm_bus_integrity	pattgen_tl_intg_err	8.000s	155.750us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	stress_all_with_rand_reset	pattgen_stress_all_with_rand_reset	42.000s	6.246ms	0	1	0.00
V3		TOTAL			0	1	0.00
	Unmapped tests	pattgen_inactive_level	10.000s	46.427us	1	1	100.00
		TOTAL			16	18	88.89

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:929) [pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:

Test pattgen_stress_all_with_rand_reset has 1 failures.

0.pattgen_stress_all_with_rand_reset.47866398025086197138729203954703718393491538368188492335995632465671461174661
Line 123, in log /nightly/runs/scratch/master/pattgen-sim-xcelium/0.pattgen_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 699808133 ps: (cip_base_vseq.sv:929) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_ERROR @ 699809243 ps: (cip_base_vseq.sv:833) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 699809243 ps: (cip_base_vseq.sv:836) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
  Issuing reset for run 1/10
  UVM_INFO @ 699847705 ps: (cip_base_vseq.sv:857) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]

UVM_ERROR (pattgen_scoreboard.sv:76) [scoreboard] exp_item_q[i] item uncompared: has 1 failures:
- Test pattgen_stress_all has 1 failures.
  - 0.pattgen_stress_all.30284006588854284323681290628531290381420440332306989378943831988137362000294
    Line 148, in log /nightly/runs/scratch/master/pattgen-sim-xcelium/0.pattgen_stress_all/latest/run.log
```
  UVM_ERROR @ 327319108 ps: (pattgen_scoreboard.sv:76) [uvm_test_top.env.scoreboard] exp_item_q[i] item uncompared:
  ------------------------------------
  Name      Type          Size  Value
  ------------------------------------
  exp_item  pattgen_item  -     @10901
```