ROM_CTRL/32KB Simulation Results

Monday May 12 2025 18:42:29 UTC

GitHub Revision: 4f742bf

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke rom_ctrl_smoke 5.390s 228.844us 1 1 100.00
V1 csr_hw_reset rom_ctrl_csr_hw_reset 5.860s 242.609us 1 1 100.00
V1 csr_rw rom_ctrl_csr_rw 4.920s 174.813us 1 1 100.00
V1 csr_bit_bash rom_ctrl_csr_bit_bash 5.490s 1.168ms 1 1 100.00
V1 csr_aliasing rom_ctrl_csr_aliasing 4.100s 168.230us 1 1 100.00
V1 csr_mem_rw_with_rand_reset rom_ctrl_csr_mem_rw_with_rand_reset 5.380s 177.950us 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr rom_ctrl_csr_rw 4.920s 174.813us 1 1 100.00
rom_ctrl_csr_aliasing 4.100s 168.230us 1 1 100.00
V1 mem_walk rom_ctrl_mem_walk 4.420s 216.096us 1 1 100.00
V1 mem_partial_access rom_ctrl_mem_partial_access 4.470s 296.659us 1 1 100.00
V1 TOTAL 8 8 100.00
V2 max_throughput_chk rom_ctrl_max_throughput_chk 5.620s 919.337us 1 1 100.00
V2 stress_all rom_ctrl_stress_all 12.300s 6.722ms 1 1 100.00
V2 kmac_err_chk rom_ctrl_kmac_err_chk 8.560s 384.690us 1 1 100.00
V2 alert_test rom_ctrl_alert_test 4.280s 386.383us 1 1 100.00
V2 tl_d_oob_addr_access rom_ctrl_tl_errors 8.210s 222.800us 1 1 100.00
V2 tl_d_illegal_access rom_ctrl_tl_errors 8.210s 222.800us 1 1 100.00
V2 tl_d_outstanding_access rom_ctrl_csr_hw_reset 5.860s 242.609us 1 1 100.00
rom_ctrl_csr_rw 4.920s 174.813us 1 1 100.00
rom_ctrl_csr_aliasing 4.100s 168.230us 1 1 100.00
rom_ctrl_same_csr_outstanding 5.210s 171.412us 1 1 100.00
V2 tl_d_partial_access rom_ctrl_csr_hw_reset 5.860s 242.609us 1 1 100.00
rom_ctrl_csr_rw 4.920s 174.813us 1 1 100.00
rom_ctrl_csr_aliasing 4.100s 168.230us 1 1 100.00
rom_ctrl_same_csr_outstanding 5.210s 171.412us 1 1 100.00
V2 TOTAL 6 6 100.00
V2S corrupt_sig_fatal_chk rom_ctrl_corrupt_sig_fatal_chk 56.110s 5.998ms 1 1 100.00
V2S passthru_mem_tl_intg_err rom_ctrl_passthru_mem_tl_intg_err 22.240s 912.171us 1 1 100.00
V2S tl_intg_err rom_ctrl_sec_cm 1.681m 712.877us 1 1 100.00
rom_ctrl_tl_intg_err 44.850s 601.773us 1 1 100.00
V2S prim_fsm_check rom_ctrl_sec_cm 1.681m 712.877us 1 1 100.00
V2S prim_count_check rom_ctrl_sec_cm 1.681m 712.877us 1 1 100.00
V2S sec_cm_checker_ctr_consistency rom_ctrl_corrupt_sig_fatal_chk 56.110s 5.998ms 1 1 100.00
V2S sec_cm_checker_ctrl_flow_consistency rom_ctrl_corrupt_sig_fatal_chk 56.110s 5.998ms 1 1 100.00
V2S sec_cm_checker_fsm_local_esc rom_ctrl_corrupt_sig_fatal_chk 56.110s 5.998ms 1 1 100.00
V2S sec_cm_compare_ctrl_flow_consistency rom_ctrl_corrupt_sig_fatal_chk 56.110s 5.998ms 1 1 100.00
V2S sec_cm_compare_ctr_consistency rom_ctrl_corrupt_sig_fatal_chk 56.110s 5.998ms 1 1 100.00
V2S sec_cm_compare_ctr_redun rom_ctrl_sec_cm 1.681m 712.877us 1 1 100.00
V2S sec_cm_fsm_sparse rom_ctrl_sec_cm 1.681m 712.877us 1 1 100.00
V2S sec_cm_mem_scramble rom_ctrl_smoke 5.390s 228.844us 1 1 100.00
V2S sec_cm_mem_digest rom_ctrl_smoke 5.390s 228.844us 1 1 100.00
V2S sec_cm_intersig_mubi rom_ctrl_smoke 5.390s 228.844us 1 1 100.00
V2S sec_cm_bus_integrity rom_ctrl_tl_intg_err 44.850s 601.773us 1 1 100.00
V2S sec_cm_bus_local_esc rom_ctrl_corrupt_sig_fatal_chk 56.110s 5.998ms 1 1 100.00
rom_ctrl_kmac_err_chk 8.560s 384.690us 1 1 100.00
V2S sec_cm_mux_mubi rom_ctrl_corrupt_sig_fatal_chk 56.110s 5.998ms 1 1 100.00
V2S sec_cm_mux_consistency rom_ctrl_corrupt_sig_fatal_chk 56.110s 5.998ms 1 1 100.00
V2S sec_cm_ctrl_redun rom_ctrl_corrupt_sig_fatal_chk 56.110s 5.998ms 1 1 100.00
V2S sec_cm_ctrl_mem_integrity rom_ctrl_passthru_mem_tl_intg_err 22.240s 912.171us 1 1 100.00
V2S sec_cm_tlul_fifo_ctr_redun rom_ctrl_sec_cm 1.681m 712.877us 1 1 100.00
V2S TOTAL 4 4 100.00
V3 stress_all_with_rand_reset rom_ctrl_stress_all_with_rand_reset 1.984m 1.750ms 1 1 100.00
V3 TOTAL 1 1 100.00
TOTAL 19 19 100.00