ROM_CTRL/64KB Simulation Results

Monday May 12 2025 18:42:29 UTC

GitHub Revision: 4f742bf

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke rom_ctrl_smoke 9.120s 299.619us 1 1 100.00
V1 csr_hw_reset rom_ctrl_csr_hw_reset 8.700s 3.381ms 1 1 100.00
V1 csr_rw rom_ctrl_csr_rw 6.980s 373.085us 1 1 100.00
V1 csr_bit_bash rom_ctrl_csr_bit_bash 6.950s 674.563us 1 1 100.00
V1 csr_aliasing rom_ctrl_csr_aliasing 6.760s 1.113ms 1 1 100.00
V1 csr_mem_rw_with_rand_reset rom_ctrl_csr_mem_rw_with_rand_reset 7.480s 607.982us 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr rom_ctrl_csr_rw 6.980s 373.085us 1 1 100.00
rom_ctrl_csr_aliasing 6.760s 1.113ms 1 1 100.00
V1 mem_walk rom_ctrl_mem_walk 6.660s 549.574us 1 1 100.00
V1 mem_partial_access rom_ctrl_mem_partial_access 7.230s 744.429us 1 1 100.00
V1 TOTAL 8 8 100.00
V2 max_throughput_chk rom_ctrl_max_throughput_chk 8.910s 1.110ms 1 1 100.00
V2 stress_all rom_ctrl_stress_all 28.400s 1.065ms 1 1 100.00
V2 kmac_err_chk rom_ctrl_kmac_err_chk 11.630s 711.917us 1 1 100.00
V2 alert_test rom_ctrl_alert_test 7.400s 296.716us 1 1 100.00
V2 tl_d_oob_addr_access rom_ctrl_tl_errors 8.080s 649.552us 1 1 100.00
V2 tl_d_illegal_access rom_ctrl_tl_errors 8.080s 649.552us 1 1 100.00
V2 tl_d_outstanding_access rom_ctrl_csr_hw_reset 8.700s 3.381ms 1 1 100.00
rom_ctrl_csr_rw 6.980s 373.085us 1 1 100.00
rom_ctrl_csr_aliasing 6.760s 1.113ms 1 1 100.00
rom_ctrl_same_csr_outstanding 7.720s 307.863us 1 1 100.00
V2 tl_d_partial_access rom_ctrl_csr_hw_reset 8.700s 3.381ms 1 1 100.00
rom_ctrl_csr_rw 6.980s 373.085us 1 1 100.00
rom_ctrl_csr_aliasing 6.760s 1.113ms 1 1 100.00
rom_ctrl_same_csr_outstanding 7.720s 307.863us 1 1 100.00
V2 TOTAL 6 6 100.00
V2S corrupt_sig_fatal_chk rom_ctrl_corrupt_sig_fatal_chk 1.513m 26.084ms 1 1 100.00
V2S passthru_mem_tl_intg_err rom_ctrl_passthru_mem_tl_intg_err 35.990s 6.659ms 1 1 100.00
V2S tl_intg_err rom_ctrl_sec_cm 2.654m 1.675ms 1 1 100.00
rom_ctrl_tl_intg_err 35.810s 326.113us 1 1 100.00
V2S prim_fsm_check rom_ctrl_sec_cm 2.654m 1.675ms 1 1 100.00
V2S prim_count_check rom_ctrl_sec_cm 2.654m 1.675ms 1 1 100.00
V2S sec_cm_checker_ctr_consistency rom_ctrl_corrupt_sig_fatal_chk 1.513m 26.084ms 1 1 100.00
V2S sec_cm_checker_ctrl_flow_consistency rom_ctrl_corrupt_sig_fatal_chk 1.513m 26.084ms 1 1 100.00
V2S sec_cm_checker_fsm_local_esc rom_ctrl_corrupt_sig_fatal_chk 1.513m 26.084ms 1 1 100.00
V2S sec_cm_compare_ctrl_flow_consistency rom_ctrl_corrupt_sig_fatal_chk 1.513m 26.084ms 1 1 100.00
V2S sec_cm_compare_ctr_consistency rom_ctrl_corrupt_sig_fatal_chk 1.513m 26.084ms 1 1 100.00
V2S sec_cm_compare_ctr_redun rom_ctrl_sec_cm 2.654m 1.675ms 1 1 100.00
V2S sec_cm_fsm_sparse rom_ctrl_sec_cm 2.654m 1.675ms 1 1 100.00
V2S sec_cm_mem_scramble rom_ctrl_smoke 9.120s 299.619us 1 1 100.00
V2S sec_cm_mem_digest rom_ctrl_smoke 9.120s 299.619us 1 1 100.00
V2S sec_cm_intersig_mubi rom_ctrl_smoke 9.120s 299.619us 1 1 100.00
V2S sec_cm_bus_integrity rom_ctrl_tl_intg_err 35.810s 326.113us 1 1 100.00
V2S sec_cm_bus_local_esc rom_ctrl_corrupt_sig_fatal_chk 1.513m 26.084ms 1 1 100.00
rom_ctrl_kmac_err_chk 11.630s 711.917us 1 1 100.00
V2S sec_cm_mux_mubi rom_ctrl_corrupt_sig_fatal_chk 1.513m 26.084ms 1 1 100.00
V2S sec_cm_mux_consistency rom_ctrl_corrupt_sig_fatal_chk 1.513m 26.084ms 1 1 100.00
V2S sec_cm_ctrl_redun rom_ctrl_corrupt_sig_fatal_chk 1.513m 26.084ms 1 1 100.00
V2S sec_cm_ctrl_mem_integrity rom_ctrl_passthru_mem_tl_intg_err 35.990s 6.659ms 1 1 100.00
V2S sec_cm_tlul_fifo_ctr_redun rom_ctrl_sec_cm 2.654m 1.675ms 1 1 100.00
V2S TOTAL 4 4 100.00
V3 stress_all_with_rand_reset rom_ctrl_stress_all_with_rand_reset 3.117m 3.307ms 1 1 100.00
V3 TOTAL 1 1 100.00
TOTAL 19 19 100.00