RV_DM/USE_JTAG_INTERFACE Simulation Results

Monday May 12 2025 18:42:29 UTC

GitHub Revision: 4f742bf

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke rv_dm_smoke 2.500s 540.114us 1 1 100.00
V1 jtag_dtm_csr_hw_reset rv_dm_jtag_dtm_csr_hw_reset 2.160s 303.152us 1 1 100.00
V1 jtag_dtm_csr_rw rv_dm_jtag_dtm_csr_rw 2.010s 184.087us 1 1 100.00
V1 jtag_dtm_csr_bit_bash rv_dm_jtag_dtm_csr_bit_bash 5.010s 2.996ms 1 1 100.00
V1 jtag_dtm_csr_aliasing rv_dm_jtag_dtm_csr_aliasing 4.030s 1.337ms 1 1 100.00
V1 jtag_dmi_csr_hw_reset rv_dm_jtag_dmi_csr_hw_reset 37.360s 18.322ms 1 1 100.00
V1 jtag_dmi_csr_rw rv_dm_jtag_dmi_csr_rw 2.220s 1.084ms 1 1 100.00
V1 jtag_dmi_csr_bit_bash rv_dm_jtag_dmi_csr_bit_bash 2.000s 1.791ms 1 1 100.00
V1 jtag_dmi_csr_aliasing rv_dm_jtag_dmi_csr_aliasing 52.790s 41.724ms 1 1 100.00
V1 jtag_dmi_cmderr_busy rv_dm_cmderr_busy 1.890s 189.768us 1 1 100.00
V1 jtag_dmi_cmderr_not_supported rv_dm_cmderr_not_supported 1.880s 138.632us 1 1 100.00
V1 cmderr_exception rv_dm_cmderr_exception 1.750s 342.461us 1 1 100.00
V1 mem_tl_access_resuming rv_dm_mem_tl_access_resuming 2.280s 500.257us 1 1 100.00
V1 mem_tl_access_halted rv_dm_mem_tl_access_halted 1.820s 484.965us 1 1 100.00
V1 cmderr_halt_resume rv_dm_cmderr_halt_resume 1.830s 142.181us 1 1 100.00
V1 dataaddr_rw_access rv_dm_dataaddr_rw_access 1.620s 80.800us 1 1 100.00
V1 halt_resume rv_dm_halt_resume_whereto 1.910s 1.193ms 1 1 100.00
V1 progbuf_busy rv_dm_cmderr_busy 1.890s 189.768us 1 1 100.00
V1 abstractcmd_status rv_dm_abstractcmd_status 1.970s 303.638us 1 1 100.00
V1 progbuf_read_write_execute rv_dm_progbuf_read_write_execute 1.920s 1.309ms 1 1 100.00
V1 progbuf_exception rv_dm_cmderr_exception 1.750s 342.461us 1 1 100.00
V1 rom_read_access rv_dm_rom_read_access 1.860s 202.389us 1 1 100.00
V1 csr_hw_reset rv_dm_csr_hw_reset 2.090s 94.080us 1 1 100.00
V1 csr_rw rv_dm_csr_rw 2.170s 486.421us 1 1 100.00
V1 csr_bit_bash rv_dm_csr_bit_bash 42.680s 4.957ms 1 1 100.00
V1 csr_aliasing rv_dm_csr_aliasing 53.210s 27.868ms 1 1 100.00
V1 csr_mem_rw_with_rand_reset rv_dm_csr_mem_rw_with_rand_reset 1.630s 62.626us 0 1 0.00
V1 regwen_csr_and_corresponding_lockable_csr rv_dm_csr_aliasing 53.210s 27.868ms 1 1 100.00
rv_dm_csr_rw 2.170s 486.421us 1 1 100.00
V1 mem_walk rv_dm_mem_walk 1.530s 148.706us 1 1 100.00
V1 mem_partial_access rv_dm_mem_partial_access 1.580s 134.642us 1 1 100.00
V1 TOTAL 26 27 96.30
V2 idcode rv_dm_smoke 2.500s 540.114us 1 1 100.00
V2 jtag_dtm_hard_reset rv_dm_jtag_dtm_hard_reset 2.600s 433.808us 1 1 100.00
V2 jtag_dtm_idle_hint rv_dm_jtag_dtm_idle_hint 1.820s 277.581us 1 1 100.00
V2 jtag_dmi_failed_op rv_dm_dmi_failed_op 1.700s 104.096us 1 1 100.00
V2 jtag_dmi_dm_inactive rv_dm_jtag_dmi_dm_inactive 2.470s 963.904us 1 1 100.00
V2 sba rv_dm_sba_tl_access 3.060s 1.692ms 1 1 100.00
rv_dm_delayed_resp_sba_tl_access 7.240s 2.603ms 0 1 0.00
V2 bad_sba rv_dm_bad_sba_tl_access 3.600s 1.092ms 1 1 100.00
V2 sba_autoincrement rv_dm_autoincr_sba_tl_access 17.910s 16.946ms 1 1 100.00
V2 jtag_dmi_debug_disabled rv_dm_jtag_dmi_debug_disabled 1.740s 103.405us 1 1 100.00
V2 sba_debug_disabled rv_dm_sba_debug_disabled 2.890s 5.225ms 1 1 100.00
V2 ndmreset_req rv_dm_ndmreset_req 2.630s 693.561us 1 1 100.00
V2 hart_unavail rv_dm_hart_unavail 1.580s 87.312us 1 1 100.00
V2 tap_ctrl_transitions rv_dm_tap_fsm 18.210s 11.407ms 0 1 0.00
rv_dm_tap_fsm_rand_reset 1.500s 14.855us 0 1 0.00
V2 hartsel_warl rv_dm_hartsel_warl 1.710s 100.408us 1 1 100.00
V2 stress_all rv_dm_stress_all 4.610s 3.190ms 1 1 100.00
V2 alert_test rv_dm_alert_test 1.660s 93.213us 1 1 100.00
V2 tl_d_oob_addr_access rv_dm_tl_errors 1.800s 133.744us 0 1 0.00
V2 tl_d_illegal_access rv_dm_tl_errors 1.800s 133.744us 0 1 0.00
V2 tl_d_outstanding_access rv_dm_csr_aliasing 53.210s 27.868ms 1 1 100.00
rv_dm_csr_hw_reset 2.090s 94.080us 1 1 100.00
rv_dm_csr_rw 2.170s 486.421us 1 1 100.00
rv_dm_same_csr_outstanding 6.540s 1.140ms 1 1 100.00
V2 tl_d_partial_access rv_dm_csr_aliasing 53.210s 27.868ms 1 1 100.00
rv_dm_csr_hw_reset 2.090s 94.080us 1 1 100.00
rv_dm_csr_rw 2.170s 486.421us 1 1 100.00
rv_dm_same_csr_outstanding 6.540s 1.140ms 1 1 100.00
V2 TOTAL 15 19 78.95
V2S tl_intg_err rv_dm_sec_cm 1.970s 637.862us 1 1 100.00
rv_dm_tl_intg_err 6.420s 968.762us 1 1 100.00
V2S sec_cm_bus_integrity rv_dm_tl_intg_err 6.420s 968.762us 1 1 100.00
V2S sec_cm_lc_hw_debug_en_intersig_mubi rv_dm_sba_debug_disabled 2.890s 5.225ms 1 1 100.00
rv_dm_debug_disabled 1.800s 51.129us 1 1 100.00
V2S sec_cm_lc_dft_en_intersig_mubi rv_dm_sba_debug_disabled 2.890s 5.225ms 1 1 100.00
rv_dm_debug_disabled 1.800s 51.129us 1 1 100.00
V2S sec_cm_otp_dis_rv_dm_late_debug_intersig_mubi rv_dm_smoke 2.500s 540.114us 1 1 100.00
V2S sec_cm_dm_en_ctrl_lc_gated rv_dm_buffered_enable 1.880s 373.163us 1 1 100.00
V2S sec_cm_sba_tl_lc_gate_fsm_sparse rv_dm_sparse_lc_gate_fsm 1.640s 278.156us 1 1 100.00
V2S sec_cm_mem_tl_lc_gate_fsm_sparse rv_dm_sparse_lc_gate_fsm 1.640s 278.156us 1 1 100.00
V2S sec_cm_exec_ctrl_mubi rv_dm_buffered_enable 1.880s 373.163us 1 1 100.00
V2S TOTAL 5 5 100.00
V3 stress_all_with_rand_reset rv_dm_stress_all_with_rand_reset 1.610s 118.637us 0 1 0.00
V3 TOTAL 0 1 0.00
Unmapped tests rv_dm_scanmode 1.460s 12.008us 1 1 100.00
TOTAL 47 53 88.68

Failure Buckets