RV_TIMER Simulation Results

Monday May 12 2025 18:42:29 UTC

GitHub Revision: 4f742bf

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	random	rv_timer_random	1.680s	12.546us	1	1	100.00
V1	csr_hw_reset	rv_timer_csr_hw_reset	1.710s	12.024us	1	1	100.00
V1	csr_rw	rv_timer_csr_rw	1.540s	14.073us	1	1	100.00
V1	csr_bit_bash	rv_timer_csr_bit_bash	3.770s	547.802us	1	1	100.00
V1	csr_aliasing	rv_timer_csr_aliasing	1.810s	23.006us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	rv_timer_csr_mem_rw_with_rand_reset	2.010s	33.911us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rv_timer_csr_rw	1.540s	14.073us	1	1	100.00
		rv_timer_csr_aliasing	1.810s	23.006us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	random_reset	rv_timer_random_reset	1.690s	343.627us	1	1	100.00
V2	disabled	rv_timer_disabled	2.560s	1.873ms	1	1	100.00
V2	cfg_update_on_fly	rv_timer_cfg_update_on_fly	1.960s	440.574us	1	1	100.00
V2	no_interrupt_test	rv_timer_cfg_update_on_fly	1.960s	440.574us	1	1	100.00
V2	stress	rv_timer_stress_all	3.020s	2.227ms	1	1	100.00
V2	alert_test	rv_timer_alert_test	1.470s	12.743us	1	1	100.00
V2	intr_test	rv_timer_intr_test	1.890s	40.591us	1	1	100.00
V2	tl_d_oob_addr_access	rv_timer_tl_errors	2.880s	413.052us	1	1	100.00
V2	tl_d_illegal_access	rv_timer_tl_errors	2.880s	413.052us	1	1	100.00
V2	tl_d_outstanding_access	rv_timer_csr_hw_reset	1.710s	12.024us	1	1	100.00
		rv_timer_csr_rw	1.540s	14.073us	1	1	100.00
		rv_timer_csr_aliasing	1.810s	23.006us	1	1	100.00
		rv_timer_same_csr_outstanding	1.710s	69.960us	1	1	100.00
V2	tl_d_partial_access	rv_timer_csr_hw_reset	1.710s	12.024us	1	1	100.00
		rv_timer_csr_rw	1.540s	14.073us	1	1	100.00
		rv_timer_csr_aliasing	1.810s	23.006us	1	1	100.00
		rv_timer_same_csr_outstanding	1.710s	69.960us	1	1	100.00
V2		TOTAL			8	8	100.00
V2S	tl_intg_err	rv_timer_sec_cm	1.760s	279.786us	1	1	100.00
		rv_timer_tl_intg_err	1.910s	102.131us	1	1	100.00
V2S	sec_cm_bus_integrity	rv_timer_tl_intg_err	1.910s	102.131us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	stress_all_with_rand_reset	rv_timer_stress_all_with_rand_reset	20.460s	11.896ms	1	1	100.00
V3		TOTAL			1	1	100.00
	Unmapped tests	rv_timer_min	1.350s	20.548us	1	1	100.00
		rv_timer_max	1.550s	43.923us	1	1	100.00
		TOTAL			19	19	100.00