SPI_DEVICE/1R1W Simulation Results

Monday May 12 2025 18:42:29 UTC

GitHub Revision: 4f742bf

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	1.909m	15.506ms	1	1	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	2.020s	23.738us	1	1	100.00
V1	csr_rw	spi_device_csr_rw	2.720s	25.017us	1	1	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	17.330s	356.788us	1	1	100.00
V1	csr_aliasing	spi_device_csr_aliasing	7.040s	1.403ms	1	1	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	2.490s	51.408us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	2.720s	25.017us	1	1	100.00
		spi_device_csr_aliasing	7.040s	1.403ms	1	1	100.00
V1	mem_walk	spi_device_mem_walk	1.580s	34.550us	1	1	100.00
V1	mem_partial_access	spi_device_mem_partial_access	2.790s	98.456us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	csb_read	spi_device_csb_read	1.770s	52.331us	1	1	100.00
V2	mem_parity	spi_device_mem_parity	1.680s	16.408us	0	1	0.00
V2	mem_cfg	spi_device_ram_cfg	2.100s	5.023us	0	1	0.00
V2	tpm_read	spi_device_tpm_rw	2.060s	36.288us	1	1	100.00
V2	tpm_write	spi_device_tpm_rw	2.060s	36.288us	1	1	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	3.950s	615.066us	1	1	100.00
		spi_device_tpm_sts_read	1.510s	19.882us	1	1	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	22.580s	4.349ms	1	1	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	2.690s	1.101ms	1	1	100.00
		spi_device_flash_all	1.680s	12.705us	1	1	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	4.530s	219.116us	1	1	100.00
		spi_device_flash_all	1.680s	12.705us	1	1	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	4.530s	219.116us	1	1	100.00
		spi_device_flash_all	1.680s	12.705us	1	1	100.00
V2	cmd_info_slots	spi_device_flash_all	1.680s	12.705us	1	1	100.00
V2	cmd_read_status	spi_device_intercept	3.050s	207.212us	1	1	100.00
		spi_device_flash_all	1.680s	12.705us	1	1	100.00
V2	cmd_read_jedec	spi_device_intercept	3.050s	207.212us	1	1	100.00
		spi_device_flash_all	1.680s	12.705us	1	1	100.00
V2	cmd_read_sfdp	spi_device_intercept	3.050s	207.212us	1	1	100.00
		spi_device_flash_all	1.680s	12.705us	1	1	100.00
V2	cmd_fast_read	spi_device_intercept	3.050s	207.212us	1	1	100.00
		spi_device_flash_all	1.680s	12.705us	1	1	100.00
V2	cmd_read_pipeline	spi_device_intercept	3.050s	207.212us	1	1	100.00
		spi_device_flash_all	1.680s	12.705us	1	1	100.00
V2	flash_cmd_upload	spi_device_upload	21.490s	18.169ms	1	1	100.00
V2	mailbox_command	spi_device_mailbox	48.110s	8.021ms	1	1	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	48.110s	8.021ms	1	1	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	48.110s	8.021ms	1	1	100.00
V2	cmd_read_buffer	spi_device_flash_mode	12.740s	3.065ms	1	1	100.00
		spi_device_read_buffer_direct	4.280s	426.282us	1	1	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	48.110s	8.021ms	1	1	100.00
		spi_device_flash_all	1.680s	12.705us	1	1	100.00
V2	quad_spi	spi_device_flash_all	1.680s	12.705us	1	1	100.00
V2	dual_spi	spi_device_flash_all	1.680s	12.705us	1	1	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	6.300s	755.089us	1	1	100.00
V2	write_enable_disable	spi_device_cfg_cmd	6.300s	755.089us	1	1	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	1.909m	15.506ms	1	1	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	4.217m	174.711ms	1	1	100.00
V2	stress_all	spi_device_stress_all	2.989m	110.730ms	1	1	100.00
V2	alert_test	spi_device_alert_test	1.540s	11.987us	1	1	100.00
V2	intr_test	spi_device_intr_test	1.470s	19.756us	1	1	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	2.530s	124.247us	1	1	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	2.530s	124.247us	1	1	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	2.020s	23.738us	1	1	100.00
		spi_device_csr_rw	2.720s	25.017us	1	1	100.00
		spi_device_csr_aliasing	7.040s	1.403ms	1	1	100.00
		spi_device_same_csr_outstanding	2.360s	74.845us	1	1	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	2.020s	23.738us	1	1	100.00
		spi_device_csr_rw	2.720s	25.017us	1	1	100.00
		spi_device_csr_aliasing	7.040s	1.403ms	1	1	100.00
		spi_device_same_csr_outstanding	2.360s	74.845us	1	1	100.00
V2		TOTAL			20	22	90.91
V2S	tl_intg_err	spi_device_sec_cm	2.110s	374.311us	1	1	100.00
		spi_device_tl_intg_err	7.230s	1.433ms	1	1	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	7.230s	1.433ms	1	1	100.00
V2S		TOTAL			2	2	100.00
	Unmapped tests	spi_device_flash_mode_ignore_cmds	3.190m	145.799ms	1	1	100.00
		TOTAL			31	33	93.94

Failure Buckets

• UVM_ERROR (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[*]) has 1 failures:

  • Test spi_device_mem_parity has 1 failures.

    • 0.spi_device_mem_parity.1257458011876394981690466997191392300846654168555130561489921420024888347557
      Line 71, in log /nightly/runs/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_mem_parity/latest/run.log

        UVM_ERROR @  13408230 ps: (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[93])
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
        UVM_ERROR @  13408230 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
        UVM_ERROR @  13408230 ps: (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[989])
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
      

• UVM_ERROR (spi_device_ram_cfg_vseq.sv:27) [spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (* [*] vs * [*]) has 1 failures:

  • Test spi_device_ram_cfg has 1 failures.

    • 0.spi_device_ram_cfg.78296293078200100851135178305238594646050946232076715937354679579413313305465
      Line 71, in log /nightly/runs/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_ram_cfg/latest/run.log

        UVM_ERROR @   2251173 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xfdff [1111110111111111] vs 0x0 [0])
        UVM_ERROR @   2265173 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x8d3d8f [100011010011110110001111] vs 0x0 [0])
        UVM_ERROR @   2342173 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xa881ae [101010001000000110101110] vs 0x0 [0])
        UVM_ERROR @   2382173 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x3c38d7 [1111000011100011010111] vs 0x0 [0])
        UVM_ERROR @   2429173 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xbd1d9c [101111010001110110011100] vs 0x0 [0])