SPI_DEVICE/2P Simulation Results

Monday May 12 2025 18:42:29 UTC

GitHub Revision: 4f742bf

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke spi_device_flash_and_tpm 10.320s 1.488ms 1 1 100.00
V1 csr_hw_reset spi_device_csr_hw_reset 2.370s 77.825us 1 1 100.00
V1 csr_rw spi_device_csr_rw 2.910s 240.793us 1 1 100.00
V1 csr_bit_bash spi_device_csr_bit_bash 9.220s 184.938us 1 1 100.00
V1 csr_aliasing spi_device_csr_aliasing 11.490s 630.758us 1 1 100.00
V1 csr_mem_rw_with_rand_reset spi_device_csr_mem_rw_with_rand_reset 2.160s 52.667us 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr spi_device_csr_rw 2.910s 240.793us 1 1 100.00
spi_device_csr_aliasing 11.490s 630.758us 1 1 100.00
V1 mem_walk spi_device_mem_walk 1.480s 13.264us 1 1 100.00
V1 mem_partial_access spi_device_mem_partial_access 2.600s 58.459us 1 1 100.00
V1 TOTAL 8 8 100.00
V2 csb_read spi_device_csb_read 1.740s 34.463us 1 1 100.00
V2 mem_parity spi_device_mem_parity 1.870s 105.920us 1 1 100.00
V2 mem_cfg spi_device_ram_cfg 1.800s 17.134us 1 1 100.00
V2 tpm_read spi_device_tpm_rw 1.770s 47.442us 1 1 100.00
V2 tpm_write spi_device_tpm_rw 1.770s 47.442us 1 1 100.00
V2 tpm_hw_reg spi_device_tpm_read_hw_reg 3.430s 519.942us 1 1 100.00
spi_device_tpm_sts_read 2.080s 120.337us 1 1 100.00
V2 tpm_fully_random_case spi_device_tpm_all 1.600s 21.472us 1 1 100.00
V2 pass_cmd_filtering spi_device_pass_cmd_filtering 4.890s 1.381ms 1 1 100.00
spi_device_flash_all 3.791m 210.511ms 1 1 100.00
V2 pass_addr_translation spi_device_pass_addr_payload_swap 4.940s 1.176ms 1 1 100.00
spi_device_flash_all 3.791m 210.511ms 1 1 100.00
V2 pass_payload_translation spi_device_pass_addr_payload_swap 4.940s 1.176ms 1 1 100.00
spi_device_flash_all 3.791m 210.511ms 1 1 100.00
V2 cmd_info_slots spi_device_flash_all 3.791m 210.511ms 1 1 100.00
V2 cmd_read_status spi_device_intercept 23.880s 38.924ms 1 1 100.00
spi_device_flash_all 3.791m 210.511ms 1 1 100.00
V2 cmd_read_jedec spi_device_intercept 23.880s 38.924ms 1 1 100.00
spi_device_flash_all 3.791m 210.511ms 1 1 100.00
V2 cmd_read_sfdp spi_device_intercept 23.880s 38.924ms 1 1 100.00
spi_device_flash_all 3.791m 210.511ms 1 1 100.00
V2 cmd_fast_read spi_device_intercept 23.880s 38.924ms 1 1 100.00
spi_device_flash_all 3.791m 210.511ms 1 1 100.00
V2 cmd_read_pipeline spi_device_intercept 23.880s 38.924ms 1 1 100.00
spi_device_flash_all 3.791m 210.511ms 1 1 100.00
V2 flash_cmd_upload spi_device_upload 19.020s 47.857ms 1 1 100.00
V2 mailbox_command spi_device_mailbox 12.450s 5.336ms 1 1 100.00
V2 mailbox_cross_outside_command spi_device_mailbox 12.450s 5.336ms 1 1 100.00
V2 mailbox_cross_inside_command spi_device_mailbox 12.450s 5.336ms 1 1 100.00
V2 cmd_read_buffer spi_device_flash_mode 3.320s 79.213us 1 1 100.00
spi_device_read_buffer_direct 6.770s 608.528us 1 1 100.00
V2 cmd_dummy_cycle spi_device_mailbox 12.450s 5.336ms 1 1 100.00
spi_device_flash_all 3.791m 210.511ms 1 1 100.00
V2 quad_spi spi_device_flash_all 3.791m 210.511ms 1 1 100.00
V2 dual_spi spi_device_flash_all 3.791m 210.511ms 1 1 100.00
V2 4b_3b_feature spi_device_cfg_cmd 4.900s 680.631us 1 1 100.00
V2 write_enable_disable spi_device_cfg_cmd 4.900s 680.631us 1 1 100.00
V2 TPM_with_flash_or_passthrough_mode spi_device_flash_and_tpm 10.320s 1.488ms 1 1 100.00
V2 tpm_and_flash_trans_with_min_inactive_time spi_device_flash_and_tpm_min_idle 5.433m 112.416ms 1 1 100.00
V2 stress_all spi_device_stress_all 3.192m 22.870ms 1 1 100.00
V2 alert_test spi_device_alert_test 1.630s 21.120us 1 1 100.00
V2 intr_test spi_device_intr_test 1.870s 17.543us 1 1 100.00
V2 tl_d_oob_addr_access spi_device_tl_errors 3.440s 55.470us 1 1 100.00
V2 tl_d_illegal_access spi_device_tl_errors 3.440s 55.470us 1 1 100.00
V2 tl_d_outstanding_access spi_device_csr_hw_reset 2.370s 77.825us 1 1 100.00
spi_device_csr_rw 2.910s 240.793us 1 1 100.00
spi_device_csr_aliasing 11.490s 630.758us 1 1 100.00
spi_device_same_csr_outstanding 3.300s 178.636us 1 1 100.00
V2 tl_d_partial_access spi_device_csr_hw_reset 2.370s 77.825us 1 1 100.00
spi_device_csr_rw 2.910s 240.793us 1 1 100.00
spi_device_csr_aliasing 11.490s 630.758us 1 1 100.00
spi_device_same_csr_outstanding 3.300s 178.636us 1 1 100.00
V2 TOTAL 22 22 100.00
V2S tl_intg_err spi_device_sec_cm 2.300s 351.944us 1 1 100.00
spi_device_tl_intg_err 13.860s 394.998us 1 1 100.00
V2S sec_cm_bus_integrity spi_device_tl_intg_err 13.860s 394.998us 1 1 100.00
V2S TOTAL 2 2 100.00
Unmapped tests spi_device_flash_mode_ignore_cmds 16.000s 4.097ms 1 1 100.00
TOTAL 33 33 100.00