SRAM_CTRL/MAIN Simulation Results

Monday May 12 2025 18:42:29 UTC

GitHub Revision: 4f742bf

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	1.077m	22.972ms	1	1	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	1.650s	15.132us	1	1	100.00
V1	csr_rw	sram_ctrl_csr_rw	1.950s	173.116us	1	1	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	2.040s	48.501us	1	1	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	1.660s	20.805us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	3.550s	692.625us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	1.950s	173.116us	1	1	100.00
		sram_ctrl_csr_aliasing	1.660s	20.805us	1	1	100.00
V1	mem_walk	sram_ctrl_mem_walk	2.114m	10.768ms	1	1	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	1.134m	6.381ms	1	1	100.00
V1		TOTAL			8	8	100.00
V2	multiple_keys	sram_ctrl_multiple_keys	3.196m	31.237ms	1	1	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	2.596m	7.503ms	1	1	100.00
V2	bijection	sram_ctrl_bijection	34.741m	755.515ms	1	1	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	3.082m	12.991ms	1	1	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	26.420s	53.736ms	1	1	100.00
V2	executable	sram_ctrl_executable	9.919m	55.547ms	1	1	100.00
V2	partial_access	sram_ctrl_partial_access	17.280s	6.244ms	1	1	100.00
		sram_ctrl_partial_access_b2b	3.521m	49.866ms	1	1	100.00
V2	max_throughput	sram_ctrl_max_throughput	40.090s	780.074us	1	1	100.00
		sram_ctrl_throughput_w_partial_write	8.270s	2.578ms	1	1	100.00
		sram_ctrl_throughput_w_readback	16.890s	797.418us	1	1	100.00
V2	regwen	sram_ctrl_regwen	10.345m	3.184ms	1	1	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	3.400s	1.263ms	1	1	100.00
V2	stress_all	sram_ctrl_stress_all	43.410m	45.044ms	1	1	100.00
V2	alert_test	sram_ctrl_alert_test	1.940s	13.442us	1	1	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	3.530s	503.254us	1	1	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	3.530s	503.254us	1	1	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	1.650s	15.132us	1	1	100.00
		sram_ctrl_csr_rw	1.950s	173.116us	1	1	100.00
		sram_ctrl_csr_aliasing	1.660s	20.805us	1	1	100.00
		sram_ctrl_same_csr_outstanding	1.700s	112.632us	1	1	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	1.650s	15.132us	1	1	100.00
		sram_ctrl_csr_rw	1.950s	173.116us	1	1	100.00
		sram_ctrl_csr_aliasing	1.660s	20.805us	1	1	100.00
		sram_ctrl_same_csr_outstanding	1.700s	112.632us	1	1	100.00
V2		TOTAL			17	17	100.00
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	15.760s	16.754ms	1	1	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	1.580s	1.726us	0	1	0.00
		sram_ctrl_tl_intg_err	2.400s	1.392ms	1	1	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	1.580s	1.726us	0	1	0.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	2.400s	1.392ms	1	1	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	10.345m	3.184ms	1	1	100.00
V2S	sec_cm_readback_config_regwen	sram_ctrl_regwen	10.345m	3.184ms	1	1	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	1.950s	173.116us	1	1	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	9.919m	55.547ms	1	1	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	9.919m	55.547ms	1	1	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	9.919m	55.547ms	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	26.420s	53.736ms	1	1	100.00
V2S	sec_cm_prim_ram_ctrl_mubi	sram_ctrl_mubi_enc_err	6.780s	686.055us	0	1	0.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	15.760s	16.754ms	1	1	100.00
V2S	sec_cm_mem_readback	sram_ctrl_readback_err	7.230s	694.787us	1	1	100.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	1.077m	22.972ms	1	1	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	1.077m	22.972ms	1	1	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	9.919m	55.547ms	1	1	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	1.580s	1.726us	0	1	0.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	26.420s	53.736ms	1	1	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	1.580s	1.726us	0	1	0.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	1.580s	1.726us	0	1	0.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	1.077m	22.972ms	1	1	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	1.580s	1.726us	0	1	0.00
V2S		TOTAL			3	5	60.00
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	12.740s	648.438us	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			29	31	93.55

Failure Buckets

• Offending 'reqfifo_rvalid' has 1 failures:

  • Test sram_ctrl_mubi_enc_err has 1 failures.

    • 0.sram_ctrl_mubi_enc_err.110973776329231279462244817154283540189973111523554116816418367567838396735332
      Line 99, in log /nightly/runs/scratch/master/sram_ctrl_main-sim-vcs/0.sram_ctrl_mubi_enc_err/latest/run.log

            Offending 'reqfifo_rvalid'
        UVM_ERROR @ 686054986 ps: (tlul_adapter_sram.sv:640) [ASSERT FAILED] rvalidHighReqFifoEmpty
        UVM_INFO @ 686054986 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: * has 1 failures:

  • Test sram_ctrl_sec_cm has 1 failures.

    • 0.sram_ctrl_sec_cm.48357753583530901381777404003635994619043011502665840265575283266410301989525
      Line 95, in log /nightly/runs/scratch/master/sram_ctrl_main-sim-vcs/0.sram_ctrl_sec_cm/latest/run.log

        UVM_ERROR @   1725896 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
        UVM_INFO @   1725896 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---