SRAM_CTRL/RET Simulation Results

Monday May 12 2025 18:42:29 UTC

GitHub Revision: 4f742bf

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	53.470s	1.184ms	1	1	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	1.580s	24.604us	1	1	100.00
V1	csr_rw	sram_ctrl_csr_rw	1.620s	21.212us	1	1	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	2.820s	462.801us	1	1	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	1.700s	78.694us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	2.000s	121.816us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	1.620s	21.212us	1	1	100.00
		sram_ctrl_csr_aliasing	1.700s	78.694us	1	1	100.00
V1	mem_walk	sram_ctrl_mem_walk	9.920s	2.191ms	1	1	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	3.130s	211.409us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	multiple_keys	sram_ctrl_multiple_keys	5.764m	33.325ms	1	1	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	2.606m	9.111ms	1	1	100.00
V2	bijection	sram_ctrl_bijection	48.420s	21.672ms	1	1	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	7.386m	13.848ms	1	1	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	3.490s	158.089us	1	1	100.00
V2	executable	sram_ctrl_executable	3.184m	1.658ms	1	1	100.00
V2	partial_access	sram_ctrl_partial_access	3.600s	53.314us	1	1	100.00
		sram_ctrl_partial_access_b2b	4.566m	19.546ms	1	1	100.00
V2	max_throughput	sram_ctrl_max_throughput	17.930s	552.978us	1	1	100.00
		sram_ctrl_throughput_w_partial_write	9.450s	79.968us	1	1	100.00
		sram_ctrl_throughput_w_readback	58.540s	1.482ms	1	1	100.00
V2	regwen	sram_ctrl_regwen	3.666m	29.215ms	1	1	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	1.620s	78.128us	1	1	100.00
V2	stress_all	sram_ctrl_stress_all	49.549m	111.963ms	1	1	100.00
V2	alert_test	sram_ctrl_alert_test	1.870s	11.786us	1	1	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	5.650s	648.259us	1	1	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	5.650s	648.259us	1	1	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	1.580s	24.604us	1	1	100.00
		sram_ctrl_csr_rw	1.620s	21.212us	1	1	100.00
		sram_ctrl_csr_aliasing	1.700s	78.694us	1	1	100.00
		sram_ctrl_same_csr_outstanding	1.630s	47.928us	1	1	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	1.580s	24.604us	1	1	100.00
		sram_ctrl_csr_rw	1.620s	21.212us	1	1	100.00
		sram_ctrl_csr_aliasing	1.700s	78.694us	1	1	100.00
		sram_ctrl_same_csr_outstanding	1.630s	47.928us	1	1	100.00
V2		TOTAL			17	17	100.00
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	3.540s	430.013us	1	1	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	1.570s	4.536us	0	1	0.00
		sram_ctrl_tl_intg_err	2.220s	114.012us	1	1	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	1.570s	4.536us	0	1	0.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	2.220s	114.012us	1	1	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	3.666m	29.215ms	1	1	100.00
V2S	sec_cm_readback_config_regwen	sram_ctrl_regwen	3.666m	29.215ms	1	1	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	1.620s	21.212us	1	1	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	3.184m	1.658ms	1	1	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	3.184m	1.658ms	1	1	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	3.184m	1.658ms	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	3.490s	158.089us	1	1	100.00
V2S	sec_cm_prim_ram_ctrl_mubi	sram_ctrl_mubi_enc_err	2.070s	40.583us	1	1	100.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	3.540s	430.013us	1	1	100.00
V2S	sec_cm_mem_readback	sram_ctrl_readback_err	1.700s	47.421us	0	1	0.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	53.470s	1.184ms	1	1	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	53.470s	1.184ms	1	1	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	3.184m	1.658ms	1	1	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	1.570s	4.536us	0	1	0.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	3.490s	158.089us	1	1	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	1.570s	4.536us	0	1	0.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	1.570s	4.536us	0	1	0.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	53.470s	1.184ms	1	1	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	1.570s	4.536us	0	1	0.00
V2S		TOTAL			3	5	60.00
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	32.840s	5.986ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			29	31	93.55

Failure Buckets

• UVM_ERROR (cip_tl_seq_item.sv:216) [req] d_user.data_intg act (*) != exp (*) has 1 failures:

  • Test sram_ctrl_readback_err has 1 failures.

    • 0.sram_ctrl_readback_err.102466111739343100058635665083212245156778178523790612695105995578023567796692
      Line 93, in log /nightly/runs/scratch/master/sram_ctrl_ret-sim-vcs/0.sram_ctrl_readback_err/latest/run.log

        UVM_ERROR @  47420692 ps: (cip_tl_seq_item.sv:216) [req] d_user.data_intg act (0x7f) != exp (0x75)
        UVM_INFO @  47420692 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: * has 1 failures:

  • Test sram_ctrl_sec_cm has 1 failures.

    • 0.sram_ctrl_sec_cm.46426479956365621473297824677995669061703366907456373807298472149598172872539
      Line 95, in log /nightly/runs/scratch/master/sram_ctrl_ret-sim-vcs/0.sram_ctrl_sec_cm/latest/run.log

        UVM_ERROR @   4535607 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
        UVM_INFO @   4535607 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---