SYSRST_CTRL Simulation Results

Monday May 12 2025 18:42:29 UTC

GitHub Revision: 4f742bf

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sysrst_ctrl_smoke	3.260s	2.115ms	1	1	100.00
V1	input_output_inverted	sysrst_ctrl_in_out_inverted	2.670s	2.479ms	1	1	100.00
V1	combo_detect_ec_rst	sysrst_ctrl_combo_detect_ec_rst	2.030s	2.529ms	1	1	100.00
V1	combo_detect_ec_rst_with_pre_cond	sysrst_ctrl_combo_detect_ec_rst_with_pre_cond	2.950s	2.532ms	1	1	100.00
V1	csr_hw_reset	sysrst_ctrl_csr_hw_reset	14.930s	6.008ms	1	1	100.00
V1	csr_rw	sysrst_ctrl_csr_rw	5.330s	2.064ms	1	1	100.00
V1	csr_bit_bash	sysrst_ctrl_csr_bit_bash	1.665m	77.046ms	1	1	100.00
V1	csr_aliasing	sysrst_ctrl_csr_aliasing	4.280s	2.783ms	1	1	100.00
V1	csr_mem_rw_with_rand_reset	sysrst_ctrl_csr_mem_rw_with_rand_reset	2.660s	2.112ms	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sysrst_ctrl_csr_rw	5.330s	2.064ms	1	1	100.00
		sysrst_ctrl_csr_aliasing	4.280s	2.783ms	1	1	100.00
V1		TOTAL			9	9	100.00
V2	combo_detect	sysrst_ctrl_combo_detect	1.439m	93.043ms	1	1	100.00
V2	combo_detect_with_pre_cond	sysrst_ctrl_combo_detect_with_pre_cond	2.324m	74.209ms	0	1	0.00
V2	auto_block_key_outputs	sysrst_ctrl_auto_blk_key_output	3.260s	3.714ms	1	1	100.00
V2	keyboard_input_triggered_interrupt	sysrst_ctrl_edge_detect	6.580s	4.345ms	1	1	100.00
V2	pin_output_keyboard_inversion_control	sysrst_ctrl_pin_override_test	6.430s	2.510ms	1	1	100.00
V2	pin_input_value_accessibility	sysrst_ctrl_pin_access_test	5.210s	2.077ms	1	1	100.00
V2	ec_power_on_reset	sysrst_ctrl_ec_pwr_on_rst	8.620s	3.331ms	1	1	100.00
V2	flash_write_protect_output	sysrst_ctrl_flash_wr_prot_out	7.480s	2.610ms	1	1	100.00
V2	ultra_low_power_test	sysrst_ctrl_ultra_low_pwr	5.600s	5.556ms	1	1	100.00
V2	sysrst_ctrl_feature_disable	sysrst_ctrl_feature_disable	39.420s	38.339ms	1	1	100.00
V2	stress_all	sysrst_ctrl_stress_all	10.600s	18.910ms	1	1	100.00
V2	alert_test	sysrst_ctrl_alert_test	5.930s	2.013ms	1	1	100.00
V2	intr_test	sysrst_ctrl_intr_test	6.380s	2.014ms	1	1	100.00
V2	tl_d_oob_addr_access	sysrst_ctrl_tl_errors	3.900s	2.310ms	1	1	100.00
V2	tl_d_illegal_access	sysrst_ctrl_tl_errors	3.900s	2.310ms	1	1	100.00
V2	tl_d_outstanding_access	sysrst_ctrl_csr_hw_reset	14.930s	6.008ms	1	1	100.00
		sysrst_ctrl_csr_rw	5.330s	2.064ms	1	1	100.00
		sysrst_ctrl_csr_aliasing	4.280s	2.783ms	1	1	100.00
		sysrst_ctrl_same_csr_outstanding	7.910s	4.500ms	1	1	100.00
V2	tl_d_partial_access	sysrst_ctrl_csr_hw_reset	14.930s	6.008ms	1	1	100.00
		sysrst_ctrl_csr_rw	5.330s	2.064ms	1	1	100.00
		sysrst_ctrl_csr_aliasing	4.280s	2.783ms	1	1	100.00
		sysrst_ctrl_same_csr_outstanding	7.910s	4.500ms	1	1	100.00
V2		TOTAL			14	15	93.33
V2S	tl_intg_err	sysrst_ctrl_sec_cm	48.420s	22.009ms	1	1	100.00
		sysrst_ctrl_tl_intg_err	14.800s	22.241ms	1	1	100.00
V2S	sec_cm_bus_integrity	sysrst_ctrl_tl_intg_err	14.800s	22.241ms	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	stress_all_with_rand_reset	sysrst_ctrl_stress_all_with_rand_reset	14.190s	6.192ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			26	27	96.30

Failure Buckets

• UVM_ERROR (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:559) [sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.wkup_req == * (* [*] vs * [*]) has 1 failures:
  • Test sysrst_ctrl_combo_detect_with_pre_cond has 1 failures.

    • 0.sysrst_ctrl_combo_detect_with_pre_cond.15289090588100528487041014027526561967035705504932898434791358047888419964766
      Line 460, in log /nightly/runs/scratch/master/sysrst_ctrl-sim-vcs/0.sysrst_ctrl_combo_detect_with_pre_cond/latest/run.log

        UVM_ERROR @ 74044034980 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:559) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.wkup_req == 1 (0 [0x0] vs 1 [0x1])
        UVM_INFO @ 74124034980 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:156) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] ec_rst_l2h_expected == 1
        UVM_INFO @ 74144034980 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:162) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] ec_rst_l2h_expected == 0
        UVM_ERROR @ 74209095168 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:570) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed rdata == intr_actions (0 [0x0] vs 8 [0x8])
        UVM_INFO @ 74209095168 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]