UART Simulation Results

Monday May 12 2025 18:42:29 UTC

GitHub Revision: 4f742bf

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	uart_smoke	2.400s	472.431us	1	1	100.00
V1	csr_hw_reset	uart_csr_hw_reset	1.650s	73.381us	1	1	100.00
V1	csr_rw	uart_csr_rw	1.570s	46.727us	1	1	100.00
V1	csr_bit_bash	uart_csr_bit_bash	2.190s	135.315us	1	1	100.00
V1	csr_aliasing	uart_csr_aliasing	1.560s	15.389us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	uart_csr_mem_rw_with_rand_reset	1.840s	220.207us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	uart_csr_rw	1.570s	46.727us	1	1	100.00
		uart_csr_aliasing	1.560s	15.389us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	base_random_seq	uart_tx_rx	11.700s	11.944ms	1	1	100.00
V2	parity	uart_smoke	2.400s	472.431us	1	1	100.00
		uart_tx_rx	11.700s	11.944ms	1	1	100.00
V2	parity_error	uart_intr	6.749m	354.931ms	1	1	100.00
		uart_rx_parity_err	50.940s	47.417ms	1	1	100.00
V2	watermark	uart_tx_rx	11.700s	11.944ms	1	1	100.00
		uart_intr	6.749m	354.931ms	1	1	100.00
V2	fifo_full	uart_fifo_full	51.980s	89.757ms	1	1	100.00
V2	fifo_overflow	uart_fifo_overflow	41.710s	128.274ms	1	1	100.00
V2	fifo_reset	uart_fifo_reset	26.130s	96.463ms	1	1	100.00
V2	rx_frame_err	uart_intr	6.749m	354.931ms	1	1	100.00
V2	rx_break_err	uart_intr	6.749m	354.931ms	1	1	100.00
V2	rx_timeout	uart_intr	6.749m	354.931ms	1	1	100.00
V2	perf	uart_perf	1.693m	17.026ms	1	1	100.00
V2	sys_loopback	uart_loopback	4.830s	2.278ms	1	1	100.00
V2	line_loopback	uart_loopback	4.830s	2.278ms	1	1	100.00
V2	rx_noise_filter	uart_noise_filter	8.480s	26.175ms	1	1	100.00
V2	rx_start_bit_filter	uart_rx_start_bit_filter	54.100s	45.684ms	1	1	100.00
V2	tx_overide	uart_tx_ovrd	12.730s	6.646ms	1	1	100.00
V2	rx_oversample	uart_rx_oversample	47.120s	8.362ms	1	1	100.00
V2	long_b2b_transfer	uart_long_xfer_wo_dly	8.546m	102.593ms	1	1	100.00
V2	stress_all	uart_stress_all	9.982m	397.722ms	1	1	100.00
V2	alert_test	uart_alert_test	1.840s	37.466us	1	1	100.00
V2	intr_test	uart_intr_test	1.610s	14.621us	1	1	100.00
V2	tl_d_oob_addr_access	uart_tl_errors	2.470s	77.255us	1	1	100.00
V2	tl_d_illegal_access	uart_tl_errors	2.470s	77.255us	1	1	100.00
V2	tl_d_outstanding_access	uart_csr_hw_reset	1.650s	73.381us	1	1	100.00
		uart_csr_rw	1.570s	46.727us	1	1	100.00
		uart_csr_aliasing	1.560s	15.389us	1	1	100.00
		uart_same_csr_outstanding	1.640s	14.221us	1	1	100.00
V2	tl_d_partial_access	uart_csr_hw_reset	1.650s	73.381us	1	1	100.00
		uart_csr_rw	1.570s	46.727us	1	1	100.00
		uart_csr_aliasing	1.560s	15.389us	1	1	100.00
		uart_same_csr_outstanding	1.640s	14.221us	1	1	100.00
V2		TOTAL			18	18	100.00
V2S	tl_intg_err	uart_sec_cm	1.870s	152.070us	1	1	100.00
		uart_tl_intg_err	1.850s	52.130us	1	1	100.00
V2S	sec_cm_bus_integrity	uart_tl_intg_err	1.850s	52.130us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	stress_all_with_rand_reset	uart_stress_all_with_rand_reset	32.210s	28.075ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			27	27	100.00